Lines Matching defs:SubVec
4494 SDValue SubVec = Op.getOperand(1);
4499 if (SubVec.isUndef())
4518 SubVec, Idx);
4522 MVT SubVecVT = SubVec.getSimpleValueType();
4537 // Merge them together, SubVec should be zero extended.
4538 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
4540 SubVec, ZeroIdx);
4541 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
4545 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT,
4546 Undef, SubVec, ZeroIdx);
4550 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4552 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
4560 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4566 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4569 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec,
4572 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
4577 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4595 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
4616 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4618 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec,
4620 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
4627 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec,
4629 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec,
4648 SubVec = DAG.getNode(ISD::OR, dl, WideOpVT, SubVec, Vec);
4651 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx);
9452 SDValue SubVec = Op.getOperand(i);
9453 if (SubVec.isUndef())
9455 if (ISD::isFreezeUndef(SubVec.getNode())) {
9457 if (SubVec.hasOneUse())
9462 else if (ISD::isBuildVectorAllZeros(SubVec.getNode()))
9517 SDValue SubVec = Op.getOperand(i);
9518 if (SubVec.isUndef())
9521 if (ISD::isBuildVectorAllZeros(SubVec.getNode()))
9535 SDValue SubVec = Op.getOperand(Idx);
9536 unsigned SubVecNumElts = SubVec.getSimpleValueType().getVectorNumElements();
9538 Op = widenSubVector(ShiftVT, SubVec, false, Subtarget, DAG, dl);
9551 SDValue SubVec = Op.getOperand(Idx);
9552 unsigned SubVecNumElts = SubVec.getSimpleValueType().getVectorNumElements();
9553 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, SubVec,
15298 SDValue SubVec =
15301 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec,
16975 SDValue SubVec =
16978 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec,
50822 SDValue SubVec = Src.getOperand(0);
50823 EVT SubVecVT = SubVec.getValueType();
50825 // The RHS of the AND should be a mask with as many bits as SubVec.
50843 if (!(IsLegalSetCC(SubVec) || (SubVec.getOpcode() == ISD::AND &&
50844 (IsLegalSetCC(SubVec.getOperand(0)) ||
50845 IsLegalSetCC(SubVec.getOperand(1))))))
50853 Ops[0] = SubVec;
58158 SDValue SubVec = N->getOperand(1);
58161 MVT SubVecVT = SubVec.getSimpleValueType();
58163 if (Vec.isUndef() && SubVec.isUndef())
58168 (SubVec.isUndef() || ISD::isBuildVectorAllZeros(SubVec.getNode())))
58174 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR &&
58175 ISD::isBuildVectorAllZeros(SubVec.getOperand(0).getNode())) {
58176 uint64_t Idx2Val = SubVec.getConstantOperandVal(2);
58179 SubVec.getOperand(1),
58187 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && IdxVal == 0 &&
58188 isNullConstant(SubVec.getOperand(1)) &&
58189 SubVec.getOperand(0).getOpcode() == ISD::INSERT_SUBVECTOR) {
58190 SDValue Ins = SubVec.getOperand(0);
58210 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR &&
58211 SubVec.getOperand(0).isUndef() && isNullConstant(SubVec.getOperand(2)))
58213 SubVec.getOperand(1), N->getOperand(2));
58217 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
58218 SubVec.getOperand(0).getSimpleValueType() == OpVT &&
58221 int ExtIdxVal = SubVec.getConstantOperandVal(1);
58233 return DAG.getVectorShuffle(OpVT, dl, Vec, SubVec.getOperand(0), Mask);
58266 if (Vec.isUndef() && IdxVal != 0 && SubVec.getOpcode() == X86ISD::VBROADCAST)
58267 return DAG.getNode(X86ISD::VBROADCAST, dl, OpVT, SubVec.getOperand(0));
58271 if (Vec.isUndef() && IdxVal != 0 && SubVec.hasOneUse() &&
58272 SubVec.getOpcode() == X86ISD::VBROADCAST_LOAD) {
58273 auto *MemIntr = cast<MemIntrinsicSDNode>(SubVec);
58286 if (IdxVal == (OpVT.getVectorNumElements() / 2) && SubVec.hasOneUse() &&
58287 Vec.getValueSizeInBits() == (2 * SubVec.getValueSizeInBits())) {
58289 auto *SubLd = dyn_cast<LoadSDNode>(SubVec);
58292 SubVec.getValueSizeInBits() / 8, 0))