Lines Matching defs:Shuffle
5938 KnownZero.getBitWidth() == NumElts && "Shuffle mask size mismatch");
6657 assert(0 <= Elt && Elt < (2 * NumElems) && "Shuffle index out of range");
10063 // The Shuffle result is as follow:
10832 assert(Mask.size() <= 64 && "Shuffle mask too big for blend mask");
11080 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
11236 // Shuffle the inputs into place.
11423 // Shuffle the input elements into the desired positions in V1 and V2 and
11864 // by performing 3 byte shifts. Shuffle combining can kick in above that.
13594 assert(Mask.size() == 8 && "Shuffle mask length doesn't match!");
14905 assert((!SimpleOnly || (!UseHiV1 && !UseHiV2)) && "Shuffle isn't simple");
15771 // Shuffle the (lowest) repeated elements in place for broadcast.
15774 // Shuffle the actual broadcast.
15889 // Shuffle each source sub-lane to its destination.
15926 if (SDValue Shuffle = ShuffleSubLanes(Scale))
15927 return Shuffle;
16955 assert(Widened128Mask.size() == 4 && "Shuffle widening mismatch");
17584 // Shuffle should be unary.
17783 SDValue Shuffle = DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask);
17789 Shuffle, ISD::SETGT);
17791 return DAG.getNode(ISD::TRUNCATE, DL, VT, Shuffle);
17988 // Shuffle mask widening should not interfere with a broadcast opportunity
18517 // Shuffle the element to the lowest element, then movss or movsh.
19927 SDValue Shuffle = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, Sub, {1,-1});
19928 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuffle, Sub);
29443 // Shuffle it back into the right order.
38626 "Shuffle index out of range");
38792 "Shuffle index out of range");
38846 const X86Subtarget &Subtarget, unsigned &Shuffle,
38857 Shuffle = X86ISD::VZEXT_MOVL;
38898 Shuffle = unsigned(
38902 Shuffle = DAG.getOpcode_EXTEND_VECTOR_INREG(Shuffle);
38916 Shuffle = X86ISD::VZEXT_MOVL;
38929 Shuffle = X86ISD::MOVDDUP;
38934 Shuffle = X86ISD::MOVSLDUP;
38939 Shuffle = X86ISD::MOVSHDUP;
38948 Shuffle = X86ISD::MOVDDUP;
38954 Shuffle = X86ISD::MOVSLDUP;
38960 Shuffle = X86ISD::MOVSHDUP;
38971 Shuffle = X86ISD::MOVDDUP;
38978 Shuffle = X86ISD::MOVSLDUP;
38985 Shuffle = X86ISD::MOVSHDUP;
39002 unsigned &Shuffle, MVT &ShuffleVT,
39016 Shuffle = X86ISD::VPERMI;
39024 Shuffle = X86ISD::VPERMI;
39032 Shuffle = X86ISD::VPERMILPI;
39062 Shuffle = (AllowIntDomain ? X86ISD::PSHUFD : X86ISD::VPERMILPI);
39083 Shuffle = X86ISD::PSHUFLW;
39097 Shuffle = X86ISD::PSHUFHW;
39112 Shuffle = X86ISD::VROTLI;
39124 matchShuffleAsShift(ShuffleVT, Shuffle, MaskScalarSizeInBits, Mask, 0,
39130 (Shuffle == X86ISD::VSHLDQ || Shuffle == X86ISD::VSRLDQ))
39150 unsigned &Shuffle, MVT &SrcVT, MVT &DstVT,
39161 Shuffle = Subtarget.hasSSE2() ? X86ISD::UNPCKL : X86ISD::MOVLHPS;
39168 Shuffle = Subtarget.hasSSE2() ? X86ISD::UNPCKH : X86ISD::MOVHLPS;
39175 Shuffle = X86ISD::MOVSD;
39181 Shuffle = X86ISD::MOVSS;
39188 Shuffle = X86ISD::MOVSH;
39198 if (matchShuffleWithPACK(MaskVT, SrcVT, V1, V2, Shuffle, Mask, DAG,
39215 Shuffle = X86ISD::PACKUS;
39222 Shuffle = X86ISD::PACKUS;
39229 Shuffle = X86ISD::PACKSS;
39241 if (matchShuffleWithUNPCK(MaskVT, V1, V2, Shuffle, IsUnary, Mask, DL, DAG,
39287 Shuffle = ISD::OR;
39331 Shuffle = ISD::OR;
39346 unsigned &Shuffle, MVT &ShuffleVT, unsigned &PermuteImm) {
39358 Shuffle = X86ISD::VALIGN;
39375 Shuffle = X86ISD::PALIGNR;
39404 Shuffle = X86ISD::BLENDI;
39412 Shuffle = X86ISD::BLENDI;
39424 Shuffle = X86ISD::INSERTPS;
39439 Shuffle = X86ISD::SHUFP;
39484 Shuffle = X86ISD::SHUFP;
39496 Shuffle = X86ISD::INSERTPS;
39784 unsigned Shuffle, PermuteImm;
39825 DAG, Subtarget, Shuffle, ShuffleSrcVT, ShuffleVT) &&
39828 if (Depth == 0 && Root.getOpcode() == Shuffle)
39831 Res = DAG.getNode(Shuffle, DL, ShuffleVT, Res);
39836 AllowIntDomain, DAG, Subtarget, Shuffle, ShuffleVT,
39840 if (Depth == 0 && Root.getOpcode() == Shuffle)
39843 Res = DAG.getNode(Shuffle, DL, ShuffleVT, Res,
39887 NewV2, DL, DAG, Subtarget, Shuffle, ShuffleSrcVT,
39890 if (Depth == 0 && Root.getOpcode() == Shuffle)
39894 Res = DAG.getNode(Shuffle, DL, ShuffleVT, NewV1, NewV2);
39902 Subtarget, Shuffle, ShuffleVT, PermuteImm) &&
39904 if (Depth == 0 && Root.getOpcode() == Shuffle)
39908 Res = DAG.getNode(Shuffle, DL, ShuffleVT, NewV1, NewV2,
40137 // Bits[2:1] - (Per Lane) PD Shuffle Mask.
40138 // Bits[2:0] - (Per Lane) PS Shuffle Mask.
40360 assert(!WideInputs.empty() && "Shuffle with no inputs detected");
40650 // Shuffle the constant bits according to the mask.
40806 // Shuffle inputs must not be larger than the shuffle result.
41017 assert(!Ops.empty() && "Shuffle with no inputs detected");
41156 if (SDValue Shuffle = combineX86ShuffleChain(
41159 return Shuffle;
42392 assert(0 <= M && M < 8 && "Shuffle index out of range");
42896 if (SDValue Shuffle = combineTargetShuffle(Op, dl, DAG, DCI, Subtarget))
42897 return Shuffle;
43707 // Shuffle inputs must be the same size as the result.
44473 "Shuffle mask index out of range");
45734 SDValue Shuffle =
45736 DP = DAG.getNode(ISD::ADD, DL, DpVT, DP, Shuffle);
45808 SDValue Shuffle =
45810 SAD = DAG.getNode(ISD::ADD, DL, SadVT, SAD, Shuffle);
46000 // Shuffle inputs must be the same size as the result.
51319 if (SDValue Shuffle = combineX86ShufflesRecursively(
51324 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Shuffle,
53328 // Shuffle folding should merge these back together.
58615 SDValue Shuffle =
58617 return extractSubVector(Shuffle, 0, DAG, DL, SizeInBits);