Lines Matching defs:SetCC
24253 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
24424 SDValue SetCC = getSETCC(Cond, Overflow, DL, DAG);
24426 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC);
26451 SDValue SetCC;
26454 SetCC = getSETCC(X86::COND_E, Comi, dl, DAG);
26459 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP);
26463 SetCC = getSETCC(X86::COND_NE, Comi, dl, DAG);
26468 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP);
26473 SetCC = getSETCC(X86::COND_A, Comi, dl, DAG);
26478 SetCC = getSETCC(X86::COND_AE, Comi, dl, DAG);
26483 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
26609 SDValue SetCC = getSETCC(X86::COND_B, Res.getValue(1), dl, DAG);
26610 SDValue Results[] = { SetCC, Res };
26781 SDValue SetCC = getSETCC(X86CC, Test, dl, DAG);
26782 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
26843 SDValue SetCC = getSETCC(X86CC, PCMP, dl, DAG);
26844 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
27411 SDValue SetCC = getSETCC(X86::COND_B, Operation.getValue(0), dl, DAG);
27412 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
27432 SDValue SetCC = getSETCC(X86::COND_E, Operation.getValue(0), dl, DAG);
27433 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
27522 SDValue SetCC = getSETCC(X86::COND_B, Operation.getValue(0), dl, DAG);
27523 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
27818 SDValue SetCC = getSETCC(X86::COND_NE, InTrans, dl, DAG);
27819 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
32678 SDValue SetCC = getSETCC(IsSigned ? X86::COND_O : X86::COND_B,
32681 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
32683 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
47822 // an SetCC or extended from it.
47826 SDValue SetCC;
47832 SetCC = Op2;
47834 SetCC = Op1;
47847 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
47848 SetCC.getOpcode() == ISD::TRUNCATE ||
47849 SetCC.getOpcode() == ISD::AND) {
47850 if (SetCC.getOpcode() == ISD::AND) {
47852 if (isOneConstant(SetCC.getOperand(0)))
47854 if (isOneConstant(SetCC.getOperand(1)))
47858 SetCC = SetCC.getOperand(OpIdx);
47861 SetCC = SetCC.getOperand(0);
47864 switch (SetCC.getOpcode()) {
47872 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
47877 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
47880 return SetCC.getOperand(1);
47883 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
47884 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
47890 SDValue Op = SetCC.getOperand(0);
47915 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
47918 return SetCC.getOperand(3);
50942 SDValue SetCC = N->getOperand(0);
50944 if (SetCC.getOpcode() != X86ISD::SETCC || !Flag.hasOneUse())
50956 SDValue X = SetCC.getOperand(1);
50962 SDValue CCN = SetCC.getOperand(0);
51149 if (SDValue SetCC = combineAndOrForCcmpCtest(N, DAG, DCI, Subtarget))
51150 return SetCC;
51926 if (SDValue SetCC = combineAndOrForCcmpCtest(N, DAG, DCI, Subtarget))
51927 return SetCC;
51954 // (0 - SetCC) | C -> (zext (not SetCC)) * (C + 1) - 1 if we can get a LEA out of it.
52067 // SetCC on x86 zero extends so only act on this if it's a logical shift.
54327 if (SDValue SetCC = foldXor1SetCC(N, DAG))
54328 return SetCC;
57218 SDValue SetCC = Op1.getOperand(0);
57219 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
57223 SDValue NewSetCC = getSETCC(NewCC, SetCC.getOperand(1), DL, DAG);
57244 SDValue SetCC = Sub.getOperand(1);
57246 if (!X86::isZeroNode(Sub.getOperand(0)) || SetCC.getOpcode() != X86ISD::SETCC)
57250 Ops[3] = SetCC.getOperand(0);
57251 Ops[4] = SetCC.getOperand(1);