Lines Matching defs:SRL
1325 setOperationAction(ISD::SRL, VT, Custom);
1533 setOperationAction(ISD::SRL, VT, Custom);
1970 setOperationAction(ISD::SRL, VT, Custom);
2654 ISD::SRL,
3543 if (ShiftOpc == ISD::SHL || ShiftOpc == ISD::SRL) {
3560 return AndMask->getSignificantBits() > 32 ? (unsigned)ISD::SRL
3566 return ShiftOrRotateAmt.uge(7) ? (unsigned)ISD::SRL : ShiftOpc;
3578 // We prefer rotate for vectors of if we won't get a zext mask with SRL
3583 // Non-vector type and we have a zext mask with SRL.
3584 return ISD::SRL;
3612 N->getOperand(0).getOpcode() == ISD::SRL) ||
3613 (N->getOpcode() == ISD::SRL &&
6368 case ISD::SRL: {
7088 case ISD::SRL:
8601 case ISD::SRL:
11575 // expanded to OR(SRL,SHL), will be more efficient, but if they can
11586 SDValue SRL = DAG.getNode(X86ISD::VSRLI, DL, RotateVT, V1,
11588 SDValue Rot = DAG.getNode(ISD::OR, DL, RotateVT, SHL, SRL);
12648 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
17893 case ISD::SRL:
18495 Res = DAG.getNode(ISD::SRL, dl, MVT::i32, Res,
18507 Res = DAG.getNode(ISD::SRL, dl, MVT::i16, Res,
19640 DAG.getNode(ISD::SRL, DL, MVT::v4i64, Src, One),
20142 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
20619 return DAG.getNode(ISD::SRL, DL, VT, Extend,
20821 /// possibly by converting a SRL node to SRA for sign extension.
20900 if (In.getOpcode() == ISD::SRL && In->hasOneUse())
23386 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
24509 case ISD::SRL:
24543 // SELECT (AND(X,1) == 0), Y, (SRL Y, Z) -> (SRL Y, (AND NEG(AND(X,1)), Z))
25657 case ISD::SRL:
25706 ShiftOpc = ISD::SRL;
28259 DAG.getNode(ISD::SRL, DL, MVT::i16,
28268 DAG.getNode(ISD::SRL, DL, MVT::i32, LUT, Shift),
28515 case ISD::SRL:
28519 return (getGFNICtrlImm(ISD::SRL, Amt) |
28522 return getGFNICtrlImm(ISD::SRL, 8 - Amt) | getGFNICtrlImm(ISD::SHL, Amt);
28524 return getGFNICtrlImm(ISD::SHL, 8 - Amt) | getGFNICtrlImm(ISD::SRL, Amt);
28608 SDValue Hi = DAG.getNode(ISD::SRL, DL, CurrVT, Op0, NibbleShift);
28651 SDValue R0 = DAG.getNode(ISD::SRL, DL, NextVT, ResNext, Shift);
28652 SDValue R1 = DAG.getNode(ISD::SRL, DL, NextVT, HiZ, Shift);
29762 assert((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
29798 assert((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
29856 // SRA upper i32, SRL whole i64 and select lower i32.
29907 if ((Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL) &&
29960 if (Op.getOpcode() == ISD::SRL) {
29962 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT, R,
29964 SRL = DAG.getBitcast(VT, SRL);
29967 return DAG.getNode(ISD::AND, dl, VT, SRL, DAG.getConstant(Mask, dl, VT));
29971 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
30007 unsigned LogicalOp = (Opcode == ISD::SHL ? ISD::SHL : ISD::SRL);
30136 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
30137 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
30147 if (Opc == ISD::SRL || Opc == ISD::SRA)
30149 if (Opc == ISD::SHL || Opc == ISD::SRL)
30221 // Constant ISD::SRA/SRL/SHL can be performed efficiently on vXiN vectors by
30320 unsigned LogicalOpc = Opc == ISD::SRA ? (unsigned)ISD::SRL : Opc;
30385 // Constant ISD::SRL can be performed efficiently on vXi16 vectors as we
30387 if (Opc == ISD::SRL && ConstantAmt &&
30495 else if (Opc == ISD::SRL)
30529 // Constant ISD::SRA/SRL can be performed efficiently on vXi8 vectors as we
30531 if (ConstantAmt && (Opc == ISD::SRA || Opc == ISD::SRL) &&
30618 if (Opc == ISD::SHL || Opc == ISD::SRL) {
30839 DAG.getNode(ISD::SRL, DL, WideVT, DAG.getBitcast(WideVT, Op1),
30850 SDValue ShY = DAG.getNode(ISD::SRL, DL, VT, Op1,
30863 unsigned ShiftOpc = IsFSHR ? ISD::SRL : ISD::SHL;
30958 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, Res, Amt);
30961 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, Res, HiShift);
31077 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, R,
31121 unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL;
31191 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL;
31192 unsigned ShiftRHS = IsROTL ? ISD::SRL : ISD::SHL;
31232 supportedVectorVarShift(VT, Subtarget, ISD::SRL);
31240 SDValue SHL = DAG.getNode(IsROTL ? ISD::SHL : ISD::SRL, DL, VT, R, Amt);
31241 SDValue SRL = DAG.getNode(IsROTL ? ISD::SRL : ISD::SHL, DL, VT, R, AmtR);
31242 return DAG.getNode(ISD::OR, DL, VT, SHL, SRL);
32100 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), ShifterV);
32135 SDValue HiNibbles = DAG.getNode(ISD::SRL, DL, VT, Op, FourV);
32216 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
32220 DAG.getNode(ISD::SRL, DL, MVT::i32, Op,
32228 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
32233 Op = DAG.getNode(ISD::SRL, DL, MVT::i32,
32245 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
32250 Op = DAG.getNode(ISD::SRL, DL, MVT::i64, LUT,
32261 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
32266 Op = DAG.getNode(ISD::SRL, DL, MVT::i32, Op,
32270 Op = DAG.getNode(ISD::SRL, DL, MVT::i32, Op,
32390 SDValue Hi = DAG.getNode(ISD::SRL, DL, VT, In, DAG.getConstant(4, DL, VT));
32441 DAG.getNode(ISD::SRL, DL, MVT::i64, X,
32449 SDValue Hi16 = DAG.getNode(ISD::SRL, DL, MVT::i32, X,
32461 DAG.getNode(ISD::SRL, DL, MVT::i32, X, DAG.getConstant(8, DL, MVT::i8)));
33313 case ISD::SRL:
33414 SDValue Op = DAG.getNode(ISD::SRL, dl, MVT::i64, N->getOperand(0),
33469 // TODO: Could use SRL+TRUNCATE but that doesn't become a PSHUFD.
34071 DAG.getNode(ISD::SRL, dl, SrcVT, Src, One),
41950 if (TruncIn.getOpcode() == ISD::SRL &&
45942 Scl = DAG.getNode(ISD::SRL, dl, SclVT, Scl,
46639 return DAG.getNode(ISD::SRL, DL, VT, Vec,
47456 // Unlike general shift instructions (SHL/SRL), AVX2's VSHLV/VSRLV handle
47465 if ((LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SHL) &&
47471 return DAG.getNode(LHS.getOpcode() == ISD::SRL ? X86ISD::VSRLV
47477 if ((RHS.getOpcode() == ISD::SRL || RHS.getOpcode() == ISD::SHL) &&
47483 return DAG.getNode(RHS.getOpcode() == ISD::SRL ? X86ISD::VSRLV
48015 if (Carry.getOpcode() == ISD::SRL) {
49267 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
49268 "SRL or SRA node is required here!");
49465 supportedVectorVarShift(VT, Subtarget, ISD::SRL)) {
49519 SDValue NewShift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1);
50633 if (!supportedVectorShiftWithImm(VT, Subtarget, ISD::SRL))
50766 SDValue LShr = DAG.getNode(ISD::SRL, dl, VT, AllOnes, Sub);
51203 // Fold AND(SRL(X,Y),1) -> SETCC(BT(X,Y), COND_B) iff Y is not a constant
51213 // Peek through AND(NOT(SRL(X,Y)),1).
51219 if (Src.getOpcode() == ISD::SRL &&
51223 // Peek through AND(SRL(NOT(X),Y),1).
51502 SDValue Scc = DAG.getNode(ISD::SRL, dl, MVT::i32, Trunc,
51645 /// Also try (ADD/SUB)+(AND(SRL,1)) bit extraction pattern with BT+{ADC, SBB}.
52047 /// XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
52069 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
56480 if ((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) &&
56487 APInt Mask = Op.getOpcode() == ISD::SRL
57789 // Special case: SHL/SRL AVX1 V4i64 by 32-bits can lower as a shuffle.
58738 case ISD::SRL:
59370 case ISD::SRL: return combineShiftRightLogical(N, DAG, DCI, Subtarget);
59579 case ISD::SRL:
59694 case ISD::SRL: {