Lines Matching defs:SBB
24360 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry.getValue(1));
24437 Opc == X86ISD::SBB || Opc == X86ISD::SMUL || Opc == X86ISD::UMUL ||
24578 SDValue SBB = DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24581 return DAG.getNode(ISD::OR, DL, VT, SBB, Y);
26592 // ADC/SBB
26599 // ADC/SBB.
32673 SDValue Sum = DAG.getNode(IsAdd ? X86ISD::ADC : X86ISD::SBB, DL, VTs,
34699 NODE_NAME_CASE(SBB)
46809 // We have a more efficient lowering for "(X == 0) ? Y : -1" using SBB.
51643 /// then try to convert it to an ADC or SBB. This replaces TEST+SET+{ADD/SUB}
51644 /// with CMP+{ADC, SBB}.
51645 /// Also try (ADD/SUB)+(AND(SRL,1)) bit extraction pattern with BT+{ADC, SBB}.
51677 // -1 + SETAE --> -1 + (!CF) --> CF ? -1 : 0 --> SBB %eax, %eax
51678 // 0 - SETB --> 0 - (CF) --> CF ? -1 : 0 --> SBB %eax, %eax
51690 // -1 + SETBE (SUB A, B) --> -1 + SETAE (SUB B, A) --> SUB + SBB
51691 // 0 - SETA (SUB A, B) --> 0 - SETB (SUB B, A) --> SUB + SBB
51706 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL,
51728 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL,
51737 return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL,
51758 return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL,
51812 // Add the flags type for ADC/SBB nodes.
51818 return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, VTs, X,
51823 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, VTs, X,
51828 /// then try to convert it to an ADC or SBB. This replaces TEST+SET+{ADD/SUB}
51829 /// with CMP+{ADC, SBB}.
56660 return DAG.getNode(X86ISD::SBB, SDLoc(N), VTs, LHS, RHS, Flags);
56663 // Fold SBB(SUB(X,Y),0,Carry) -> SBB(X,Y,Carry)
56667 return DAG.getNode(X86ISD::SBB, SDLoc(N), N->getVTList(), LHS.getOperand(0),
57293 // Fold SUB(X,ADC(Y,0,W)) -> SBB(X,Y,W)
57297 return DAG.getNode(X86ISD::SBB, SDLoc(Op1), Op1->getVTList(), Op0,
57301 // Fold SUB(X,SBB(Y,Z,W)) -> SUB(ADC(X,Z,W),Y)
57303 if (Op1.getOpcode() == X86ISD::SBB && Op1->hasOneUse() &&
59365 case X86ISD::SBB: return combineSBB(N, DAG);