Lines Matching defs:RepeatedMask

9685 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
9691                                   SmallVectorImpl<int> &RepeatedMask) {
9693   RepeatedMask.assign(LaneSize, -1);
9707     if (RepeatedMask[i % LaneSize] < 0)
9709       RepeatedMask[i % LaneSize] = LocalM;
9710     else if (RepeatedMask[i % LaneSize] != LocalM)
9720                                 SmallVectorImpl<int> &RepeatedMask) {
9721   return isRepeatedShuffleMask(128, VT, Mask, RepeatedMask);
9726   SmallVector<int, 32> RepeatedMask;
9727   return isRepeatedShuffleMask(128, VT, Mask, RepeatedMask);
9733                                 SmallVectorImpl<int> &RepeatedMask) {
9734   return isRepeatedShuffleMask(256, VT, Mask, RepeatedMask);
9742                                         SmallVectorImpl<int> &RepeatedMask) {
9744   RepeatedMask.assign(LaneSize, SM_SentinelUndef);
9751       if (!isUndefOrZero(RepeatedMask[i % LaneSize]))
9753       RepeatedMask[i % LaneSize] = SM_SentinelZero;
9764     if (RepeatedMask[i % LaneSize] == SM_SentinelUndef)
9766       RepeatedMask[i % LaneSize] = LocalM;
9767     else if (RepeatedMask[i % LaneSize] != LocalM)
9778                                         SmallVectorImpl<int> &RepeatedMask) {
9780                                      Mask, RepeatedMask);
10944     SmallVector<int, 8> RepeatedMask;
10945     if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10947       assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
10950         if (RepeatedMask[i] >= 8)
11693   SmallVector<int, 16> RepeatedMask;
11694   if (!is128BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask))
11697   int Rotation = matchShuffleAsElementRotate(V1, V2, RepeatedMask);
11703   int NumElts = RepeatedMask.size();
15876     SmallVector<int, 8> RepeatedMask((unsigned)NumElts, -1);
15885         RepeatedMask[Idx] = M + (Lane * NumLaneElts);
15901     if (RepeatedMask == Mask || SubLaneMask == Mask)
15905         DAG.getVectorShuffle(VT, DL, V1, V2, RepeatedMask);
16278     SmallVector<int, 2> RepeatedMask;
16279     if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
16281       narrowShuffleMaskElts(2, RepeatedMask, PSHUFDMask);
16391   SmallVector<int, 4> RepeatedMask;
16392   if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
16393     assert(RepeatedMask.size() == 4 &&
16397     if (isShuffleEquivalent(RepeatedMask, {0, 0, 2, 2}, V1, V2))
16399     if (isShuffleEquivalent(RepeatedMask, {1, 1, 3, 3}, V1, V2))
16404                          getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
16412     return lowerShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
16538   SmallVector<int, 4> RepeatedMask;
16540       is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask);
16542     assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
16545                          getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
16600   if (Is128BitLaneRepeatedShuffle && isSingleSHUFPSMask(RepeatedMask)) {
16603     SDValue ShufPS = lowerShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask,
16701     SmallVector<int, 8> RepeatedMask;
16702     if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
16707           DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
17070     SmallVector<int, 4> RepeatedMask;
17071     if (is256BitLaneRepeatedShuffleMask(MVT::v8f64, Mask, RepeatedMask))
17073                          getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
17110   SmallVector<int, 4> RepeatedMask;
17111   if (is128BitLaneRepeatedShuffleMask(MVT::v16f32, Mask, RepeatedMask)) {
17112     assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
17115     if (isShuffleEquivalent(RepeatedMask, {0, 0, 2, 2}, V1, V2))
17117     if (isShuffleEquivalent(RepeatedMask, {1, 1, 3, 3}, V1, V2))
17122                          getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
17133     return lowerShuffleWithSHUFPS(DL, MVT::v16f32, RepeatedMask, V1, V2, DAG);
17272   SmallVector<int, 4> RepeatedMask;
17274       is128BitLaneRepeatedShuffleMask(MVT::v16i32, Mask, RepeatedMask);
17276     assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
17279                          getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
17310   if (Is128BitLaneRepeatedShuffle && isSingleSHUFPSMask(RepeatedMask)) {
17313     SDValue ShufPS = lowerShuffleWithSHUFPS(DL, MVT::v16f32, RepeatedMask,
17379     SmallVector<int, 8> RepeatedMask;
17380     if (is128BitLaneRepeatedShuffleMask(MVT::v32i16, Mask, RepeatedMask)) {
17385                                                  RepeatedMask, Subtarget, DAG);
39022         SmallVector<int, 4> RepeatedMask;
39023         if (is256BitLaneRepeatedShuffleMask(MVT::v8f64, Mask, RepeatedMask)) {
39026           PermuteImm = getV4X86ShuffleImm(RepeatedMask);
39055         SmallVector<int, 4> RepeatedMask;
39056         if (is128BitLaneRepeatedShuffleMask(MaskEltVT, Mask, RepeatedMask)) {
39058           SmallVector<int, 4> WordMask = RepeatedMask;
39060             narrowShuffleMaskElts(2, RepeatedMask, WordMask);
39075         SmallVector<int, 4> RepeatedMask;
39076         if (is128BitLaneRepeatedShuffleMask(MaskEltVT, Mask, RepeatedMask)) {
39077           ArrayRef<int> LoMask(RepeatedMask.data() + 0, 4);
39078           ArrayRef<int> HiMask(RepeatedMask.data() + 4, 4);
39393         SmallVector<int, 8> RepeatedMask;
39395                                         RepeatedMask)) {
39396           assert(RepeatedMask.size() == 8 &&
39400             if (RepeatedMask[i] >= 8)
39450     SmallVector<int, 4> RepeatedMask;
39451     if (isRepeatedTargetShuffleMask(128, MaskVT, Mask, RepeatedMask)) {
39455         int M0 = RepeatedMask[Offset];
39456         int M1 = RepeatedMask[Offset + 1];
39458         if (isUndefInRange(RepeatedMask, Offset, 2)) {
39460         } else if (isUndefOrZeroInRange(RepeatedMask, Offset, 2)) {