Lines Matching defs:Promote
205 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
260 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
262 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
263 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i8, Promote);
264 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
265 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i16, Promote);
275 // Promote i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
277 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
278 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i8, Promote);
291 // Promote i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
293 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
295 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i8, Promote);
307 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
309 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i8, Promote);
310 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
312 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i16, Promote);
424 // Promote the i8 variants and force them on up to i32 which has a shorter
699 setF16Action(MVT::f16, Promote);
700 setOperationAction(ISD::FADD, MVT::f16, Promote);
701 setOperationAction(ISD::FSUB, MVT::f16, Promote);
702 setOperationAction(ISD::FMUL, MVT::f16, Promote);
703 setOperationAction(ISD::FDIV, MVT::f16, Promote);
708 setOperationAction(ISD::STRICT_FADD, MVT::f16, Promote);
709 setOperationAction(ISD::STRICT_FSUB, MVT::f16, Promote);
710 setOperationAction(ISD::STRICT_FMUL, MVT::f16, Promote);
711 setOperationAction(ISD::STRICT_FDIV, MVT::f16, Promote);
712 setOperationAction(ISD::STRICT_FMA, MVT::f16, Promote);
713 setOperationAction(ISD::STRICT_FMINNUM, MVT::f16, Promote);
714 setOperationAction(ISD::STRICT_FMAXNUM, MVT::f16, Promote);
715 setOperationAction(ISD::STRICT_FMINIMUM, MVT::f16, Promote);
716 setOperationAction(ISD::STRICT_FMAXIMUM, MVT::f16, Promote);
717 setOperationAction(ISD::STRICT_FSQRT, MVT::f16, Promote);
718 setOperationAction(ISD::STRICT_FPOW, MVT::f16, Promote);
719 setOperationAction(ISD::STRICT_FLDEXP, MVT::f16, Promote);
720 setOperationAction(ISD::STRICT_FLOG, MVT::f16, Promote);
721 setOperationAction(ISD::STRICT_FLOG2, MVT::f16, Promote);
722 setOperationAction(ISD::STRICT_FLOG10, MVT::f16, Promote);
723 setOperationAction(ISD::STRICT_FEXP, MVT::f16, Promote);
724 setOperationAction(ISD::STRICT_FEXP2, MVT::f16, Promote);
725 setOperationAction(ISD::STRICT_FCEIL, MVT::f16, Promote);
726 setOperationAction(ISD::STRICT_FFLOOR, MVT::f16, Promote);
727 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f16, Promote);
728 setOperationAction(ISD::STRICT_FRINT, MVT::f16, Promote);
729 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Promote);
730 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Promote);
731 setOperationAction(ISD::STRICT_FROUND, MVT::f16, Promote);
732 setOperationAction(ISD::STRICT_FROUNDEVEN, MVT::f16, Promote);
733 setOperationAction(ISD::STRICT_FTRUNC, MVT::f16, Promote);
2299 setOperationAction(ISD::FREM, MVT::f16, Promote);
2300 setOperationAction(ISD::STRICT_FREM, MVT::f16, Promote);
2303 setOperationAction(ISD::STRICT_FROUND, MVT::f16, Promote);
2630 setOperationAction(Op, MVT::f32, Promote);
2638 setOperationAction(Op, MVT::f32, Promote);
20253 // Promote i32 to i64 and use a signed conversion on 64-bit targets.
21524 // Promote i32 to i64 and use a signed operation on 64-bit targets.
21547 // Promote i16 to i32 if we can use a SSE operation or the type is f128.
21691 // Promote result of FP_TO_*INT to at least 32 bits.
21697 // Promote conversions to unsigned 32-bit to 64-bit, because it will allow
33725 // Promote the input to 128 bits. Type legalization will turn this into
54958 // We do not want i16 CMOV's. Promote to i32 and truncate afterwards.
55004 if (SDValue Promote = PromoteMaskArithmetic(N0, dl, DAG, Subtarget))
55005 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Promote, N1);