Lines Matching defs:OpMask

40800   SmallVector<int, 64> OpMask;
40804   if (getTargetShuffleInputs(Op, OpDemandedElts, OpInputs, OpMask, OpUndef,
40819     OpMask.assign(NumElts, SM_SentinelUndef);
40820     std::iota(OpMask.begin(), OpMask.end(), ExtractIdx);
40830     unsigned OpMaskSize = OpMask.size();
40833       for (int &M : OpMask) {
40843     OpMask.append((NumSubVecs - 1) * OpMaskSize, SM_SentinelUndef);
40857       for (int i = 0, e = OpMask.size(); i != e; ++i) {
40858         int M = OpMask[i];
40861         UsedInputs.setBit(M / OpMask.size());
40868     resolveTargetShuffleFromZeroables(OpMask, OpUndef, OpZero,
40871     Mask = OpMask;
40874     resolveTargetShuffleFromZeroables(OpMask, OpUndef, OpZero);
40900     assert(((RootMask.size() > OpMask.size() &&
40901              RootMask.size() % OpMask.size() == 0) ||
40902             (OpMask.size() > RootMask.size() &&
40903              OpMask.size() % RootMask.size() == 0) ||
40904             OpMask.size() == RootMask.size()) &&
40912     assert(llvm::has_single_bit<uint32_t>(OpMask.size()) &&
40915     unsigned OpMaskSizeLog2 = llvm::countr_zero(OpMask.size());
40917     unsigned MaskWidth = std::max<unsigned>(OpMask.size(), RootMask.size());
40919         std::max<unsigned>(1, OpMask.size() >> RootMaskSizeLog2);
40959       if (OpMask[OpIdx] < 0) {
40962         Mask[i] = OpMask[OpIdx];
40967       unsigned OpMaskedIdx = OpRatio == 1 ? OpMask[OpIdx]
40968                                           : (OpMask[OpIdx] << OpRatioLog2) +
40972       int InputIdx = OpMask[OpIdx] / (int)OpMask.size();
43701   SmallVector<int, 64> OpMask;
43703   if (!getTargetShuffleInputs(Op, DemandedElts, OpInputs, OpMask, OpUndef,
43708   if (OpMask.size() != (unsigned)NumElts ||
43722       OpMask[i] = SM_SentinelUndef;
43724   if (isUndefInRange(OpMask, 0, NumElts)) {
43728   if (isUndefOrZeroInRange(OpMask, 0, NumElts)) {
43734     if (isSequentialOrUndefInRange(OpMask, 0, NumElts, Src * NumElts))
43747         int M = OpMask[i] - Lo;
60017     // Conditional OpMask regs (AVX512)