Lines Matching defs:N10

42341       SDValue N10 = N1.getOperand(0);
42343       if (N10 == N0 ||
42345         if (N10 != N0)
42346           std::swap(N10, N11);
42349         N10 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SVT, N10, ZeroIdx);
42351         SDValue Scl = DAG.getNode(Opcode1, DL, SVT, N10, N11);
50429   SDValue N10 = N1.getOperand(0);
50431   EVT N10Type = N10.getValueType();
50441     SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
50460   // logic (setcc N00, N01), (setcc N10, N11) -->
50461   // extelt (logic (setcc (s2v N00), (s2v N01)), setcc (s2v N10), (s2v N11))), 0
50470   SDValue Vec10 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, N10);
51629   SDValue N10 = N1->getOperand(0);
51631   if (SDValue Result = foldMaskedMergeImpl(N00, N01, N10, N11, DL, DAG))
51633   if (SDValue Result = foldMaskedMergeImpl(N01, N00, N10, N11, DL, DAG))
51635   if (SDValue Result = foldMaskedMergeImpl(N10, N11, N00, N01, DL, DAG))
51637   if (SDValue Result = foldMaskedMergeImpl(N11, N10, N00, N01, DL, DAG))
53755   SDValue N10 = N1.getOperand(0);
53763     std::swap(N10, N11);
53768       N10.getOpcode() != ISD::ZERO_EXTEND ||
53775   N10 = N10.getOperand(0);
53781       N10.getValueType().getVectorElementType() != MVT::i8 ||
53788       N10.getOpcode() != ISD::BUILD_VECTOR ||
53792   // N00/N10 are zero extended. N01/N11 are sign extended.
53804     SDValue N10Elt = N10.getOperand(i);
56857   SDValue N00, N01, N10, N11;
56859                          m_Mul(m_SExt(m_Value(N10)), m_SExt(m_Value(N11))))))
56865       N10.getValueType() != InVT || N11.getValueType() != InVT)
56871       N10.getOpcode() != ISD::BUILD_VECTOR ||
56885     SDValue N10Elt = N10.getOperand(i);