Lines Matching defs:Masked

10978     if (SDValue Masked = lowerShuffleAsBitMask(DL, VT, V1, V2, Mask, Zeroable,
10980       return Masked;
11045       if (SDValue Masked = lowerShuffleAsBitMask(DL, VT, V1, V2, Mask, Zeroable,
11047         return Masked;
13524   if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask,
13526     return Masked;
14233   if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask,
14235     return Masked;
14589   if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask,
14591     return Masked;
17451   if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v64i8, V1, V2, Mask,
17453     return Masked;
27288 /// Emit Masked Truncating Store with signed or unsigned saturation.
30336       SDValue Masked = DAG.getNode(ISD::AND, dl, WideVT, ShiftedR, Mask);
30337       Masked = DAG.getBitcast(VT, Masked);
30340         return Masked;
30352       //   (Masked ^ SignBitMask) - SignBitMask
30355       //   Masked + SignBitMask - SignBitMask
30357       // This is equal to Masked which is what we want: the sign bit was clear
30361       //   Masked - SignBitmask - SignBitMask
30363       // This is equal to Masked - 2*SignBitMask which will correctly sign
30370           DAG.getNode(ISD::XOR, dl, VT, Masked, SignBitMask);