Lines Matching defs:KnownUndef
5749 APInt &KnownUndef, APInt &KnownZero) {
5751 KnownUndef = KnownZero = APInt::getZero(Size);
5767 KnownUndef.setBit(i);
5789 KnownUndef.setBit(i);
5818 KnownUndef.setBit(i);
5832 APInt &KnownUndef, APInt &KnownZero) {
5844 KnownUndef = KnownZero = APInt::getZero(Size);
5871 KnownUndef.setBit(i);
5884 KnownUndef.setBit(i);
5897 KnownUndef.setBit(i);
5912 KnownUndef.setBit(i);
5920 KnownUndef.setBit(i);
5933 const APInt &KnownUndef,
5937 assert(KnownUndef.getBitWidth() == NumElts &&
5941 if (KnownUndef[i])
5950 APInt &KnownUndef,
5953 KnownUndef = KnownZero = APInt::getZero(NumElts);
5958 KnownUndef.setBit(i);
6547 APInt &KnownUndef, APInt &KnownZero,
6557 if (getTargetShuffleAndZeroables(Op, Mask, Inputs, KnownUndef, KnownZero)) {
6559 resolveTargetShuffleFromZeroables(Mask, KnownUndef, KnownZero);
6564 resolveZeroablesFromTargetShuffle(Mask, KnownUndef, KnownZero);
6575 APInt KnownUndef, KnownZero;
6576 return getTargetShuffleInputs(Op, DemandedElts, Inputs, Mask, KnownUndef,
17970 APInt KnownUndef, KnownZero;
17971 computeZeroableShuffleElements(OrigMask, V1, V2, KnownUndef, KnownZero);
17973 APInt Zeroable = KnownUndef | KnownZero;
39794 APInt KnownUndef, KnownZero;
39795 resolveZeroablesFromTargetShuffle(Mask, KnownUndef, KnownZero);
39796 APInt Zeroable = KnownUndef | KnownZero;
42994 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero,
43187 if (SimplifyDemandedVectorElts(Src, DemandedSrc, KnownUndef, KnownZero, TLO,
43191 KnownUndef <<= ShiftAmt;
43226 if (SimplifyDemandedVectorElts(Src, DemandedSrc, KnownUndef, KnownZero, TLO,
43230 KnownUndef.lshrInPlace(ShiftAmt);
43392 KnownUndef = SrcUndef.zextOrTrunc(NumElts);
43422 KnownUndef = LHSUndef & RHSUndef;
43716 KnownUndef = OpUndef;
43725 KnownUndef.setAllBits();
44061 APInt KnownUndef, KnownZero;
44063 if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef,
44192 APInt KnownUndef, KnownZero;
44194 if (SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef, KnownZero,