Lines Matching defs:IsROTL

30991   bool IsROTL = Opcode == ISD::ROTL;
31007       unsigned RotOpc = IsROTL ? X86ISD::VROTLI : X86ISD::VROTRI;
31019     unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR;
31025   if (!IsROTL) {
31054     assert(IsROTL && "Only ROTL expected");
31073     uint64_t ShlAmt = IsROTL ? RotAmt : (EltSizeInBits - RotAmt);
31074     uint64_t SrlAmt = IsROTL ? (EltSizeInBits - RotAmt) : RotAmt;
31106         unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR;
31109       unsigned ShiftX86Opc = IsROTL ? X86ISD::VSHLI : X86ISD::VSRLI;
31116       return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL);
31121   unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL;
31136     return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL);
31161       if (IsROTL)
31186     if (!IsROTL && !useVPTERNLOG(Subtarget, VT)) {
31188       IsROTL = true;
31191     unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL;
31192     unsigned ShiftRHS = IsROTL ? ISD::SRL : ISD::SHL;
31240     SDValue SHL = DAG.getNode(IsROTL ? ISD::SHL : ISD::SRL, DL, VT, R, Amt);
31241     SDValue SRL = DAG.getNode(IsROTL ? ISD::SRL : ISD::SHL, DL, VT, R, AmtR);
31246   if (!IsROTL) {
31248     IsROTL = true;
31254   assert(IsROTL && "Only ROTL supported");