Lines Matching defs:IdxVal
4067 static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
4081 IdxVal &= ~(ElemsPerChunk - 1);
4086 Vec->ops().slice(IdxVal, ElemsPerChunk));
4090 Vec.getOperand(1).getValueType().getVectorNumElements() <= IdxVal &&
4094 SDValue VecIdx = DAG.getVectorIdxConstant(IdxVal, dl);
4104 static SDValue extract128BitVector(SDValue Vec, unsigned IdxVal,
4108 return extractSubVector(Vec, IdxVal, DAG, dl, 128);
4112 static SDValue extract256BitVector(SDValue Vec, unsigned IdxVal,
4115 return extractSubVector(Vec, IdxVal, DAG, dl, 256);
4118 static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4136 IdxVal &= ~(ElemsPerChunk - 1);
4138 SDValue VecIdx = DAG.getVectorIdxConstant(IdxVal, dl);
4148 static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4151 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4496 unsigned IdxVal = Op.getConstantOperandVal(2);
4502 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4514 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(Vec.getNode())) {
4524 assert(IdxVal + SubVecNumElems <= NumElems &&
4525 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4530 if (IdxVal == 0) {
4549 assert(IdxVal != 0 && "Unexpected index");
4551 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
4556 assert(IdxVal != 0 && "Unexpected index");
4558 if (llvm::all_of(Vec->ops().slice(IdxVal + SubVecNumElems),
4561 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
4565 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4576 if (IdxVal + SubVecNumElems == NumElems) {
4578 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
4591 SDValue ShiftBits = DAG.getTargetConstant(NumElems - IdxVal, dl, MVT::i8);
4607 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4611 APInt Mask0 = APInt::getBitsSet(NumElems, IdxVal, IdxVal + SubVecNumElems);
4633 unsigned LowShift = NumElems - IdxVal;
4640 unsigned HighShift = IdxVal + SubVecNumElems;
18270 // If IdxVal is 0, it's cheaper to do a move instead of a pextrb, unless
18278 unsigned IdxVal = Idx->getAsZExtVal();
18280 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
18340 unsigned IdxVal = IdxC->getZExtValue();
18341 if (IdxVal == 0) // the operation is legal
18349 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
18435 unsigned IdxVal = IdxC->getZExtValue();
18441 Vec = extract128BitVector(Vec, IdxVal, DAG, dl);
18447 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
18449 IdxVal &= ElemsPerChunk - 1;
18451 DAG.getVectorIdxConstant(IdxVal, dl));
18459 // If IdxVal is 0, it's cheaper to do a move instead of a pextrw, unless
18461 if (IdxVal == 0 && !X86::mayFoldIntoZeroExtend(Op) &&
18472 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
18488 int DWordIdx = IdxVal / 4;
18493 int ShiftVal = (IdxVal % 4) * 8;
18500 int WordIdx = IdxVal / 2;
18505 int ShiftVal = (IdxVal % 2) * 8;
18514 if (IdxVal == 0)
18519 Mask[0] = static_cast<int>(IdxVal);
18529 if (IdxVal == 0)
18625 uint64_t IdxVal = N2C->getZExtValue();
18639 CstVectorElts[IdxVal] = OnesCst;
18649 BlendMask.push_back(i == IdxVal ? i + NumElts : i);
18661 if (VT.is256BitVector() && IdxVal == 0) {
18680 if (IdxVal >= NumEltsIn128 &&
18687 BlendMask.push_back(i == IdxVal ? i + NumElts : i);
18692 SDValue V = extract128BitVector(N0, IdxVal, DAG, dl);
18696 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
18702 return insert128BitVector(N0, V, IdxVal, DAG, dl);
18707 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(N0.getNode())) {
18740 N2 = DAG.getTargetConstant(IdxVal, dl, MVT::i8);
18756 if (IdxVal == 0 && (!MinSize || !X86::mayFoldLoad(N1, Subtarget))) {
18771 DAG.getTargetConstant(IdxVal << 4, dl, MVT::i8));
18835 uint64_t IdxVal = Op.getConstantOperandVal(1);
18837 if (IdxVal == 0) // the operation is legal
18845 DAG.getTargetConstant(IdxVal, dl, MVT::i8));
58160 uint64_t IdxVal = N->getConstantOperandVal(2);
58180 DAG.getVectorIdxConstant(IdxVal + Idx2Val, dl));
58187 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && IdxVal == 0 &&
58219 (IdxVal != 0 ||
58231 Mask[i + IdxVal] = i + ExtIdxVal + VecNumElts;
58266 if (Vec.isUndef() && IdxVal != 0 && SubVec.getOpcode() == X86ISD::VBROADCAST)
58271 if (Vec.isUndef() && IdxVal != 0 && SubVec.hasOneUse() &&
58286 if (IdxVal == (OpVT.getVectorNumElements() / 2) && SubVec.hasOneUse() &&
58375 unsigned IdxVal = N->getConstantOperandVal(1);
58419 return DAG.getBuildVector(VT, DL, InVec->ops().slice(IdxVal, NumSubElts));
58422 if (IdxVal != 0 && InVec.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
58425 unsigned NewIdx = IdxVal + InVec.getConstantOperandVal(1);
58435 IdxVal == InVec.getConstantOperandVal(2) &&
58439 unsigned NewIdxVal = InVec.getConstantOperandVal(2) - IdxVal;
58448 if (IdxVal != 0 && (InVec.getOpcode() == X86ISD::VBROADCAST ||
58454 if (IdxVal != 0 && InVec.getOpcode() == X86ISD::SUBV_BROADCAST_LOAD &&
58459 if ((InSizeInBits % SizeInBits) == 0 && (IdxVal % NumSubElts) == 0) {
58467 unsigned SubVecIdx = IdxVal / NumSubElts;
58500 if (IdxVal == 0 && VT == MVT::v2f64 && InVecVT == MVT::v4f64) {
58526 extractSubVector(Src, IdxVal, DAG, DL, SizeInBits));
58528 if (IdxVal == 0 &&
58538 if (IdxVal == 0 && InOpcode == ISD::VSELECT &&
58547 if (IdxVal == 0 && InOpcode == ISD::TRUNCATE && Subtarget.hasVLX() &&
58560 extractSubVector(InVec.getOperand(0), IdxVal, DAG, DL, SizeInBits));
58565 M = VT.getScalarSizeInBits() < 64 ? M : (M >> IdxVal);
58567 extractSubVector(InVec.getOperand(0), IdxVal, DAG,
58579 extractSubVector(InVec.getOperand(0), IdxVal, DAG,
58581 extractSubVector(InVec.getOperand(1), IdxVal, DAG,
58588 extractSubVector(InVec.getOperand(0), IdxVal, DAG,
58590 extractSubVector(InVec.getOperand(1), IdxVal, DAG,
58598 M = VT.getScalarType() == MVT::i16 ? M : (M >> IdxVal);
58600 extractSubVector(InVec.getOperand(0), IdxVal, DAG,
58602 extractSubVector(InVec.getOperand(1), IdxVal, DAG,
58608 if (IdxVal != 0) {
58612 Mask = extractSubVector(Mask, IdxVal, DAG, DL, SizeInBits);
58630 extractSubVector(InVec.getOperand(0), IdxVal, DAG, DL, SizeInBits);