Lines Matching defs:FalseOp

48468   SDValue FalseOp = N->getOperand(0);
48474   if (TrueOp == FalseOp)
48480     if (!(FalseOp.getValueType() == MVT::f80 ||
48481           (FalseOp.getValueType() == MVT::f64 && !Subtarget.hasSSE2()) ||
48482           (FalseOp.getValueType() == MVT::f32 && !Subtarget.hasSSE1())) ||
48484       SDValue Ops[] = {FalseOp, TrueOp, DAG.getTargetConstant(CC, DL, MVT::i8),
48494     if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
48500         std::swap(TrueOp, FalseOp);
48598           CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
48600         std::swap(TrueOp, FalseOp);
48604         SDValue Ops[] = {FalseOp, Cond.getOperand(0),
48618   if (CC == X86::COND_AE && isOneConstant(FalseOp) &&
48659         std::swap(FalseOp, TrueOp);
48664       SDValue LOps[] = {FalseOp, TrueOp,
48681     SDValue Const = FalseOp;
57034   SDValue FalseOp = Cmov.getOperand(0);
57052     FalseOp = DAG.getNode(ISD::ADD, DL, VT, X, FalseOp);
57054     Cmov = DAG.getNode(X86ISD::CMOV, DL, VT, FalseOp, TrueOp,
57060   FalseOp = DAG.getNode(ISD::ADD, DL, VT, OtherOp, FalseOp);
57062   return DAG.getNode(X86ISD::CMOV, DL, VT, FalseOp, TrueOp, Cmov.getOperand(2),
57166   SDValue FalseOp = N1.getOperand(0);
57178     if (!(TrueOp == X && FalseOp == NegX) && !(TrueOp == NegX && FalseOp == X))
57182     SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VT, TrueOp, FalseOp,
57192       (FalseOp == Cond.getValue(0) || TrueOp == Cond.getValue(0)) &&
57194       (FalseOp.getOpcode() == ISD::SUB || FalseOp.getOpcode() == X86ISD::SUB) &&
57195       (TrueOp.getOperand(0) == FalseOp.getOperand(1)) &&
57196       (TrueOp.getOperand(1) == FalseOp.getOperand(0))) {
57198     return DAG.getNode(X86ISD::CMOV, DL, VT, TrueOp, FalseOp, N1.getOperand(2),