Lines Matching defs:DCI
41763 TargetLowering::DAGCombinerInfo &DCI,
41769 TargetLowering::DAGCombinerInfo &DCI,
41792 DCI.CombineTo(N.getNode(), Movddup);
41794 DCI.recursivelyDeleteUnusedNodes(LN);
41893 DCI.CombineTo(N.getNode(), BcastLd);
41896 DCI.recursivelyDeleteUnusedNodes(LN);
41900 DCI.CombineTo(LN, Scl, BcastLd.getValue(1));
41924 DCI.CombineTo(N.getNode(), BcastLd);
41926 DCI.recursivelyDeleteUnusedNodes(Src.getNode());
41941 DCI.CombineTo(N.getNode(), BcastLd);
41943 DCI.recursivelyDeleteUnusedNodes(Src.getNode());
41970 DCI.CombineTo(N.getNode(), BcastLd);
41972 DCI.recursivelyDeleteUnusedNodes(Src.getNode());
41987 DCI.CombineTo(N.getNode(), BcastLd);
41989 DCI.recursivelyDeleteUnusedNodes(LN);
42007 DCI.CombineTo(N.getNode(), BcastLd);
42009 DCI.recursivelyDeleteUnusedNodes(LN);
42025 DCI.CombineTo(N.getNode(), VZLoad);
42027 DCI.recursivelyDeleteUnusedNodes(LN);
42043 DCI.CombineTo(N.getNode(), VZLoad);
42045 DCI.recursivelyDeleteUnusedNodes(LN);
42094 if (!DCI.isBeforeLegalizeOps() && N0.hasOneUse()) {
42474 combineConcatVectorOps(DL, WideVT, Ops, DAG, DCI, Subtarget)) {
42507 combineConcatVectorOps(DL, VT, Ops, DAG, DCI, Subtarget)) {
42864 TargetLowering::DAGCombinerInfo &DCI,
42896 if (SDValue Shuffle = combineTargetShuffle(Op, dl, DAG, DCI, Subtarget))
42910 if (TLI.SimplifyDemandedVectorElts(Op, DemandedElts, DCI))
44823 TargetLowering::DAGCombinerInfo &DCI,
44827 if (!DCI.isBeforeLegalizeOps())
45048 TargetLowering::DAGCombinerInfo &DCI,
45061 if (DCI.isBeforeLegalize()) {
45107 } else if (DCI.isAfterLegalizeDAG()) {
45285 if (SDValue V = combineCastedMaskArithmetic(N, DAG, DCI, Subtarget))
45834 TargetLowering::DAGCombinerInfo &DCI) {
45851 DCI.isAfterLegalizeDAG() && !LikelyUsedAsVector && LoadVec->isSimple()) {
45870 TargetLowering::DAGCombinerInfo &DCI,
45872 if (DCI.isBeforeLegalizeOps())
46065 N, SrcVT, peekThroughBitcasts(SrcOp), ExtractIdx, dl, DAG, DCI))
46075 TargetLowering::DAGCombinerInfo &DCI) {
46112 if (DCI.isBeforeLegalize() && Vec.getOpcode() == ISD::VSELECT &&
46371 TargetLowering::DAGCombinerInfo &DCI,
46373 if (SDValue NewOp = combineExtractWithShuffle(N, DAG, DCI, Subtarget))
46422 DCI))
46478 if (SDValue V = scalarizeExtEltFP(N, DAG, Subtarget, DCI))
46484 dl, DAG, DCI))
46525 DCI.CombineTo(Use, Res);
46536 if (DCI.isBeforeLegalize() && TLI.isTypeLegal(TruncSVT)) {
46550 TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) {
46554 if (!DCI.isBeforeLegalizeOps())
46648 TargetLowering::DAGCombinerInfo &DCI,
46859 TargetLowering::DAGCombinerInfo &DCI,
46917 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
46918 !DCI.isBeforeLegalizeOps());
46934 DCI.AddToWorklist(U);
46936 DCI.CommitTargetLoweringOpt(TLO);
47042 TargetLowering::DAGCombinerInfo &DCI,
47078 if (CondConstantVector && DCI.isBeforeLegalizeOps() &&
47447 ISD::SIGN_EXTEND, DL, ExtCondVT, Cond, DAG, DCI, Subtarget)) {
47493 if (SDValue V = combineVSelectWithAllOnesOrZeros(N, DAG, DL, DCI, Subtarget))
47496 if (SDValue V = combineVSelectToBLENDV(N, DAG, DL, DCI, Subtarget))
47539 (DCI.isBeforeLegalize() || (VT != MVT::v64i1 || Subtarget.is64Bit()))) {
47541 if (DCI.isBeforeLegalize() || TLI.isTypeLegal(IntVT)) {
47568 if (DCI.isBeforeLegalize() && !Subtarget.hasAVX512() &&
48464 TargetLowering::DAGCombinerInfo &DCI,
48588 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
48589 // the DCI.xxxx conditions are provided to postpone the optimization as
49086 TargetLowering::DAGCombinerInfo &DCI,
49097 if (DCI.isBeforeLegalize() && VT.isVector())
49127 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
49450 TargetLowering::DAGCombinerInfo &DCI,
49485 if (!DCI.isAfterLegalizeDAG())
49670 TargetLowering::DAGCombinerInfo &DCI,
49821 TargetLowering::DAGCombinerInfo &DCI,
49869 TargetLowering::DAGCombinerInfo &DCI,
49895 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
49902 TargetLowering::DAGCombinerInfo &DCI,
50048 DCI))
50055 TargetLowering::DAGCombinerInfo &DCI,
50076 APInt::getAllOnes(NumBitsPerElt), DCI))
50081 if (VT.isSimple() && DCI.isAfterLegalizeDAG()) {
50094 TargetLowering::DAGCombinerInfo &DCI,
50419 TargetLowering::DAGCombinerInfo &DCI,
50439 if (N0.getOpcode() == ISD::BITCAST && !DCI.isBeforeLegalizeOps()) {
50926 TargetLowering::DAGCombinerInfo &DCI,
50982 DCI.CombineTo(BrCond, NewBrCond);
50987 TargetLowering::DAGCombinerInfo &DCI,
51067 TargetLowering::DAGCombinerInfo &DCI,
51149 if (SDValue SetCC = combineAndOrForCcmpCtest(N, DAG, DCI, Subtarget))
51165 DAG, DCI, Subtarget))
51171 if (DCI.isBeforeLegalizeOps())
51174 if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget))
51274 if (TLI.SimplifyDemandedVectorElts(N0, Elts0, DCI) ||
51275 TLI.SimplifyDemandedVectorElts(N1, Elts1, DCI) ||
51276 TLI.SimplifyDemandedBits(N0, Bits0, Elts0, DCI) ||
51277 TLI.SimplifyDemandedBits(N1, Bits1, Elts1, DCI)) {
51279 DCI.AddToWorklist(N);
51515 TargetLowering::DAGCombinerInfo &DCI,
51517 if (DCI.isBeforeLegalize() || !Subtarget.getTargetLowering()->isCtlzFast())
51887 TargetLowering::DAGCombinerInfo &DCI,
51926 if (SDValue SetCC = combineAndOrForCcmpCtest(N, DAG, DCI, Subtarget))
51939 DAG, DCI, Subtarget))
51942 if (DCI.isBeforeLegalizeOps())
51945 if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget))
52026 return TLI.SimplifyDemandedVectorElts(OtherOp, DemandedElts, DCI);
52030 DCI.AddToWorklist(N);
52331 TargetLowering::DAGCombinerInfo &DCI,
52393 return DCI.CombineTo(N, Extract, SDValue(User, 1));
52405 TargetLowering::DAGCombinerInfo &DCI,
52418 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
52447 return DCI.CombineTo(N, NewVec, TF, true);
52453 RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) {
52462 return DCI.CombineTo(N, BoolVec, IntLoad.getValue(1), true);
52484 return DCI.CombineTo(N, Extract, SDValue(User, 1));
52489 if (SDValue V = combineConstantPoolLoads(Ld, dl, DAG, DCI, Subtarget))
52578 TargetLowering::DAGCombinerInfo &DCI,
52614 return DCI.CombineTo(ML, Insert, Load.getValue(1), true);
52619 TargetLowering::DAGCombinerInfo &DCI) {
52639 return DCI.CombineTo(ML, Blend, VecLd.getValue(1), true);
52663 return DCI.CombineTo(ML, Blend, NewML.getValue(1), true);
52667 TargetLowering::DAGCombinerInfo &DCI,
52677 reduceMaskedLoadToScalarLoad(Mld, DAG, DCI, Subtarget))
52682 if (SDValue Blend = combineMaskedLoadConstantMask(Mld, DAG, DCI))
52693 if (TLI.SimplifyDemandedBits(Mask, DemandedBits, DCI)) {
52695 DCI.AddToWorklist(N);
52746 TargetLowering::DAGCombinerInfo &DCI,
52767 if (TLI.SimplifyDemandedBits(Mask, DemandedBits, DCI)) {
52769 DCI.AddToWorklist(N);
52794 TargetLowering::DAGCombinerInfo &DCI,
52847 if (!DCI.isBeforeLegalize() && VT == MVT::v64i1 && !Subtarget.is64Bit()) {
52941 St->getValue().hasOneUse() && !DCI.isBeforeLegalizeOps()) {
53127 TargetLowering::DAGCombinerInfo &DCI,
53140 if (TLI.SimplifyDemandedVectorElts(StoredVal, DemandedElts, DCI)) {
53142 DCI.AddToWorklist(N);
53911 TargetLowering::DAGCombinerInfo &DCI) {
53923 if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI))
54085 TargetLowering::DAGCombinerInfo &DCI,
54113 bool LegalOperations = !DCI.isBeforeLegalizeOps();
54290 TargetLowering::DAGCombinerInfo &DCI,
54318 DAG, DCI, Subtarget))
54324 if (DCI.isBeforeLegalizeOps())
54377 return combineFneg(N, DAG, DCI, Subtarget);
54381 TargetLowering::DAGCombinerInfo &DCI,
54391 (DCI.isBeforeLegalize() ||
54409 TargetLowering::DAGCombinerInfo &DCI,
54433 TargetLowering::DAGCombinerInfo &DCI,
54443 if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI))
54534 TargetLowering::DAGCombinerInfo &DCI,
54546 if (SDValue NewVal = combineFneg(N, DAG, DCI, Subtarget))
54641 TargetLowering::DAGCombinerInfo &DCI) {
54646 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
54663 DCI.CombineTo(N, Convert);
54665 DCI.recursivelyDeleteUnusedNodes(LN);
54674 TargetLowering::DAGCombinerInfo &DCI) {
54695 DCI.CombineTo(N, Convert, Convert.getValue(1));
54699 DCI.CombineTo(N, Convert);
54702 DCI.recursivelyDeleteUnusedNodes(LN);
54712 TargetLowering::DAGCombinerInfo &DCI,
54746 if (DCI.isAfterLegalizeDAG() && N0.getOpcode() == ISD::SIGN_EXTEND) {
54821 if (TLI.SimplifyDemandedVectorElts(N0, Elts0, DCI) ||
54822 TLI.SimplifyDemandedVectorElts(N1, Elts1, DCI) ||
54823 TLI.SimplifyDemandedBits(N0, Bits0, Elts0, DCI) ||
54824 TLI.SimplifyDemandedBits(N1, Bits1, Elts1, DCI)) {
54826 DCI.AddToWorklist(N);
54857 TargetLowering::DAGCombinerInfo &DCI) {
54863 if (DAG.getTargetLoweringInfo().SimplifyDemandedBits(N1, DemandedMask, DCI)) {
54865 DCI.AddToWorklist(N);
54873 TargetLowering::DAGCombinerInfo &DCI) {
54880 if (TLI.SimplifyDemandedVectorElts(Src, DemandedElts, DCI)) {
54882 DCI.AddToWorklist(N);
54895 DCI.CombineTo(N, Convert, Convert.getValue(1));
54899 DCI.CombineTo(N, Convert);
54903 DCI.recursivelyDeleteUnusedNodes(LN);
55188 TargetLowering::DAGCombinerInfo &DCI,
55195 if (!DCI.isBeforeLegalizeOps() &&
55200 DCI.CombineTo(N, Setcc);
55205 DCI.CombineTo(N0.getNode(), Trunc);
55214 if (!DCI.isBeforeLegalizeOps())
55221 DAG, DCI, Subtarget))
55293 TargetLowering::DAGCombinerInfo &DCI,
55327 auto invertIfNegative = [&DAG, &TLI, &DCI](SDValue &V) {
55329 bool LegalOperations = !DCI.isBeforeLegalizeOps();
55385 TargetLowering::DAGCombinerInfo &DCI) {
55390 bool LegalOperations = !DCI.isBeforeLegalizeOps();
55408 TargetLowering::DAGCombinerInfo &DCI,
55416 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ANY_EXTEND &&
55421 DCI.CombineTo(N, Setcc);
55426 DCI.CombineTo(N0.getNode(), Trunc);
55435 if (DCI.isBeforeLegalizeOps())
55440 DAG, DCI, Subtarget))
55450 if (SDValue R = combineOrCmpEqZeroToCtlzSrl(N, DAG, DCI, Subtarget))
55487 TargetLowering::DAGCombinerInfo &DCI,
55550 isa<ConstantSDNode>(RHS) && !DCI.isBeforeLegalize()) {
55776 TargetLowering::DAGCombinerInfo &DCI,
55886 if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI))
55893 TargetLowering::DAGCombinerInfo &DCI,
55901 if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI))
55908 TargetLowering::DAGCombinerInfo &DCI) {
55916 if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI)) {
55918 DCI.AddToWorklist(N);
55951 TargetLowering::DAGCombinerInfo &DCI) {
55959 if (DCI.isBeforeLegalize()) {
56033 if (DCI.isBeforeLegalizeOps()) {
56049 if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI)) {
56051 DCI.AddToWorklist(N);
56248 TargetLowering::DAGCombinerInfo &DCI,
56313 if (DCI.isBeforeLegalize() || TruncVT != MVT::v2i32) {
56458 TargetLowering::DAGCombinerInfo &DCI,
56474 combineX86SubCmpForFlags(N, SDValue(N, 0), DAG, DCI, Subtarget))
56605 TargetLowering::DAGCombinerInfo &DCI,
56618 if (SDValue CMP = combineX86SubCmpForFlags(N, SDValue(N, 1), DAG, DCI, ST))
56640 DCI.CombineTo(GenericAddSub, Op);
56675 TargetLowering::DAGCombinerInfo &DCI) {
56702 return DCI.CombineTo(N, Res1, CarryOut);
57067 TargetLowering::DAGCombinerInfo &DCI,
57259 TargetLowering::DAGCombinerInfo &DCI,
57391 TargetLowering::DAGCombinerInfo &DCI,
58111 TargetLowering::DAGCombinerInfo &DCI,
58139 DCI, Subtarget))
58147 TargetLowering::DAGCombinerInfo &DCI,
58149 if (DCI.isBeforeLegalizeOps())
58241 combineConcatVectorOps(dl, OpVT, SubVectorOps, DAG, DCI, Subtarget))
58358 TargetLowering::DAGCombinerInfo &DCI,
58403 if (DCI.isBeforeLegalizeOps())
58776 TargetLowering::DAGCombinerInfo &DCI,
58793 if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnes(64), DCI))
58829 TargetLowering::DAGCombinerInfo &DCI) {
58867 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
58874 TargetLowering::DAGCombinerInfo &DCI,
58884 if (!DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(In.getNode()) &&
58918 if (!DCI.isBeforeLegalizeOps() && Opcode == ISD::ZERO_EXTEND_VECTOR_INREG &&
58942 TargetLowering::DAGCombinerInfo &DCI) {
58969 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
59001 TargetLowering::DAGCombinerInfo &DCI,
59010 if (DCI.isAfterLegalizeDAG() && Src.getOpcode() == ISD::FP_ROUND &&
59098 TargetLowering::DAGCombinerInfo &DCI) {
59127 return DCI.CombineTo(N, Extract, SDValue(User, 1));
59246 TargetLowering::DAGCombinerInfo &DCI) {
59249 if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnes(NumBits), DCI))
59294 TargetLowering::DAGCombinerInfo &DCI) {
59295 if (!DCI.isBeforeLegalize())
59308 TargetLowering::DAGCombinerInfo &DCI) {
59309 if (!DCI.isBeforeLegalize())
59322 TargetLowering::DAGCombinerInfo &DCI) {
59323 if (!DCI.isBeforeLegalize())
59336 DAGCombinerInfo &DCI) const {
59337 SelectionDAG &DAG = DCI.DAG;
59346 return combineExtractVectorElt(N, DAG, DCI, Subtarget);
59348 return combineCONCAT_VECTORS(N, DAG, DCI, Subtarget);
59350 return combineINSERT_SUBVECTOR(N, DAG, DCI, Subtarget);
59352 return combineEXTRACT_SUBVECTOR(N, DAG, DCI, Subtarget);
59355 case X86ISD::BLENDV: return combineSelect(N, DAG, DCI, Subtarget);
59356 case ISD::BITCAST: return combineBitcast(N, DAG, DCI, Subtarget);
59357 case X86ISD::CMOV: return combineCMov(N, DAG, DCI, Subtarget);
59358 case X86ISD::CMP: return combineCMP(N, DAG, DCI, Subtarget);
59359 case ISD::ADD: return combineAdd(N, DAG, DCI, Subtarget);
59360 case ISD::SUB: return combineSub(N, DAG, DCI, Subtarget);
59362 case X86ISD::SUB: return combineX86AddSub(N, DAG, DCI, Subtarget);
59366 case X86ISD::ADC: return combineADC(N, DAG, DCI);
59367 case ISD::MUL: return combineMul(N, DAG, DCI, Subtarget);
59370 case ISD::SRL: return combineShiftRightLogical(N, DAG, DCI, Subtarget);
59371 case ISD::AND: return combineAnd(N, DAG, DCI, Subtarget);
59372 case ISD::OR: return combineOr(N, DAG, DCI, Subtarget);
59373 case ISD::XOR: return combineXor(N, DAG, DCI, Subtarget);
59374 case ISD::BITREVERSE: return combineBITREVERSE(N, DAG, DCI, Subtarget);
59378 case ISD::AVGFLOORU: return combineAVG(N, DAG, DCI, Subtarget);
59380 case X86ISD::BEXTRI: return combineBEXTR(N, DAG, DCI, Subtarget);
59381 case ISD::LOAD: return combineLoad(N, DAG, DCI, Subtarget);
59382 case ISD::MLOAD: return combineMaskedLoad(N, DAG, DCI, Subtarget);
59383 case ISD::STORE: return combineStore(N, DAG, DCI, Subtarget);
59384 case ISD::MSTORE: return combineMaskedStore(N, DAG, DCI, Subtarget);
59386 return combineVEXTRACT_STORE(N, DAG, DCI, Subtarget);
59389 return combineSIntToFP(N, DAG, DCI, Subtarget);
59399 case ISD::FNEG: return combineFneg(N, DAG, DCI, Subtarget);
59401 case X86ISD::VTRUNC: return combineVTRUNC(N, DAG, DCI);
59402 case X86ISD::ANDNP: return combineAndnp(N, DAG, DCI, Subtarget);
59406 case X86ISD::FOR: return combineFOr(N, DAG, DCI, Subtarget);
59412 case X86ISD::CVTUI2P: return combineX86INT_TO_FP(N, DAG, DCI);
59419 return combineCVTP2I_CVTTP2I(N, DAG, DCI);
59421 case X86ISD::CVTPH2PS: return combineCVTPH2PS(N, DAG, DCI);
59422 case X86ISD::BT: return combineBT(N, DAG, DCI);
59424 case ISD::ZERO_EXTEND: return combineZext(N, DAG, DCI, Subtarget);
59425 case ISD::SIGN_EXTEND: return combineSext(N, DAG, DCI, Subtarget);
59430 return combineEXTEND_VECTOR_INREG(N, DAG, DCI, Subtarget);
59431 case ISD::SETCC: return combineSetCC(N, DAG, DCI, Subtarget);
59435 case X86ISD::PACKUS: return combineVectorPack(N, DAG, DCI, Subtarget);
59439 case X86ISD::FHSUB: return combineVectorHADDSUB(N, DAG, DCI, Subtarget);
59443 return combineVectorShiftVar(N, DAG, DCI, Subtarget);
59447 return combineVectorShiftImm(N, DAG, DCI, Subtarget);
59450 case X86ISD::PINSRW: return combineVectorInsert(N, DAG, DCI, Subtarget);
59485 case ISD::VECTOR_SHUFFLE: return combineShuffle(N, DAG, DCI,Subtarget);
59497 case ISD::STRICT_FMA: return combineFMA(N, DAG, DCI, Subtarget);
59501 case X86ISD::FMSUBADD: return combineFMADDSUB(N, DAG, DCI);
59502 case X86ISD::MOVMSK: return combineMOVMSK(N, DAG, DCI, Subtarget);
59503 case X86ISD::TESTP: return combineTESTP(N, DAG, DCI, Subtarget);
59505 case X86ISD::MSCATTER: return combineX86GatherScatter(N, DAG, DCI);
59507 case ISD::MSCATTER: return combineGatherScatter(N, DAG, DCI);
59511 case X86ISD::PMULUDQ: return combinePMULDQ(N, DAG, DCI, Subtarget);
59513 case X86ISD::VPMADDWD: return combineVPMADD(N, DAG, DCI);
59515 case X86ISD::KSHIFTR: return combineKSHIFT(N, DAG, DCI);
59518 case ISD::FP_EXTEND: return combineFP_EXTEND(N, DAG, DCI, Subtarget);
59522 case X86ISD::SUBV_BROADCAST_LOAD: return combineBROADCAST_LOAD(N, DAG, DCI);
59524 case X86ISD::PDEP: return combinePDEP(N, DAG, DCI);
59525 case ISD::INTRINSIC_WO_CHAIN: return combineINTRINSIC_WO_CHAIN(N, DAG, DCI);
59526 case ISD::INTRINSIC_W_CHAIN: return combineINTRINSIC_W_CHAIN(N, DAG, DCI);
59527 case ISD::INTRINSIC_VOID: return combineINTRINSIC_VOID(N, DAG, DCI);