Lines Matching defs:CMP
22717 return DAG.getNode(X86ISD::CMP, DL, MVT::i32,
22721 return DAG.getNode(X86ISD::CMP, DL, MVT::i32,
22774 return DAG.getNode(X86ISD::CMP, DL, MVT::i32, V,
22813 return DAG.getNode(X86ISD::CMP, DL, MVT::i32, V,
22818 // to CMP(MOVMSK(PCMPEQB(X,Y))).
23015 // Emit a CMP with 0, which is the TEST pattern.
23016 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
23074 // Emit a CMP with 0, which is the TEST pattern.
23075 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
23160 // Use SUB instead of CMP to enable CSE between SUB and CMP.
24219 // Try to use the carry flag from the add in place of an separate CMP for:
24432 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
24603 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
24688 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
24696 // handle to keep the CMP with 0. This should be removed by
24742 // If condition flag is set by a X86ISD::CMP, then use it as the condition
29935 SDValue CMP = DAG.getSetCC(dl, MVT::v64i1, Zeros, R, ISD::SETGT);
29936 return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, CMP);
32426 SDValue Flags = DAG.getNode(X86ISD::CMP, DL, MVT::i32, X,
34559 NODE_NAME_CASE(CMP)
47626 // This combine only operates on CMP-like nodes.
47627 if (!(Cmp.getOpcode() == X86ISD::CMP ||
47751 if (Cmp.getOpcode() == X86ISD::CMP) {
47752 // CMP(X,0) -> signbit test
47792 return DAG.getNode(X86ISD::CMP, DL, MVT::i32, Mask,
47801 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
47802 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
47805 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
47806 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
47812 // This combine only operates on CMP-like nodes.
47813 if (!(Cmp.getOpcode() == X86ISD::CMP ||
47821 // Check CMP operands. One of them should be 0 or 1 and the other should be
47932 if (Cond->getOpcode() == X86ISD::CMP) {
48166 return DAG.getNode(X86ISD::CMP, DL, MVT::i32, Res,
48215 if (CmpOpcode != X86ISD::CMP && CmpOpcode != X86ISD::SUB)
48241 bool IsAnyOf = CmpOpcode == X86ISD::CMP && CmpVal.isZero();
48242 bool IsAllOf = (CmpOpcode == X86ISD::SUB || CmpOpcode == X86ISD::CMP) &&
48260 // inserting an AND mask between the new MOVMSK and the CMP.
48271 return DAG.getNode(X86ISD::CMP, DL, MVT::i32,
48292 return DAG.getNode(X86ISD::CMP, DL, MVT::i32,
48351 return DAG.getNode(X86ISD::CMP, DL, MVT::i32, Result,
48377 return DAG.getNode(X86ISD::CMP, DL, MVT::i32, Result,
48411 return DAG.getNode(X86ISD::CMP, DL, MVT::i32, Result, EFLAGS.getOperand(1));
48578 // of CMOV and CMP.
48593 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
48679 Cond.getOpcode() == X86ISD::CMP && isNullConstant(Cond.getOperand(1))) {
50091 /// reference the same FP CMP, and rewrite for CMPEQSS and friends. Likewise for
50098 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
50107 // The SETCCs should both refer to the same CMP.
51013 if (Opc == X86ISD::CMP && isNullConstant(Op.getOperand(1)))
51020 // AND/OR is commutable. Canonicalize the operands to make SETCC with SUB/CMP
51036 // CMP/TEST is executed and updates the EFLAGS normally only when SrcCC
51053 // Replace any uses of the old flag produced by SUB/CMP with the new one
51535 N->getOperand(1).getOpcode() == X86ISD::CMP &&
51644 /// with CMP+{ADC, SBB}.
51767 if (EFLAGS.getOpcode() != X86ISD::CMP || !EFLAGS.hasOneUse() ||
51829 /// with CMP+{ADC, SBB}.
56464 // If we have a CMP of a truncated binop, see if we can make a smaller binop
56473 if (SDValue CMP =
56475 return CMP;
56493 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
56523 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
56534 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Src,
56553 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
56595 // For AND, keep a CMP so that we can match the test pattern.
56597 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
56618 if (SDValue CMP = combineX86SubCmpForFlags(N, SDValue(N, 1), DAG, DCI, ST))
56619 return CMP;
59358 case X86ISD::CMP: return combineCMP(N, DAG, DCI, Subtarget);