Lines Matching defs:CMOV
3388 // Speculate cttz only if we can directly use TZCNT/CMOV, can promote to
3397 // Speculate ctlz only if we can directly use LZCNT/CMOV, or can rely on BSR
23332 // Only perform this transform if CMOV is supported otherwise the select
24821 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, T1.getValueType(), T2, T1,
24827 // Or finally, promote i8 cmovs if we have CMOV,
24829 // FIXME: we should not limit promotion of i8 case to only when the CMOV is
24831 // being inserted between two CMOV's. (in i16 case too TBN)
24839 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, MVT::i32, Ops);
24843 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
24846 return DAG.getNode(X86ISD::CMOV, DL, Op.getValueType(), Ops, Op->getFlags());
27739 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl, Op->getValueType(1), Ops);
28711 // Skip CMOV if we're using a pass through value.
28717 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
28749 // Skip CMOV if src is never zero or we're using a pass through value.
28757 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
28853 // Since X86 does not have CMOV for 8-bit integer, we don't convert
28854 // 8-bit integer abs to NEG and CMOV.
28860 return DAG.getNode(X86ISD::CMOV, DL, VT, Ops);
29108 return DAG.getNode(X86ISD::CMOV, dl, VT, Diff1, Diff0,
29123 SDValue AbsDiff = DAG.getNode(X86ISD::CMOV, dl, WideVT, Diff1, Diff0,
34576 NODE_NAME_CASE(CMOV)
35700 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
35701 // together with other CMOV pseudo-opcodes into a single basic-block with
35769 // If this CMOV we are generating is the opposite condition from
35872 // We lower cascaded CMOV into two successive branches to the same block.
35885 // For a cascaded CMOV, we lower it to two successive branches to
35939 // FirstInsertedMBB (the True operand of the SELECT_CC/CMOV nodes).
35967 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
35969 // point to select the true and false operands of the CMOV in the PHI.
35971 // The code also handles two different cases of multiple CMOV opcodes
35981 // t2 = CMOV cond1 t1, f1
35982 // t3 = CMOV cond1 t2, f2
35999 // CMOV ((CMOV F, T, cc1), T, cc2) is checked here and handled by a separate
36008 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
36055 // Transfer any debug instructions inside the CMOV sequence to the sunk block.
36086 // Now remove the CMOV(s).
38420 case X86ISD::CMOV: {
38761 case X86ISD::CMOV: {
44236 case X86ISD::CMOV: {
46829 // without that, the sequence should be cheaper than a CMOV alternative.
47534 // to integer and use an integer select which will be converted to a CMOV.
47809 // where Op could be BRCOND or CMOV.
47881 case X86ISD::CMOV: {
48462 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
48486 return DAG.getNode(X86ISD::CMOV, DL, VT, Ops);
48578 // of CMOV and CMP.
48606 return DAG.getNode(X86ISD::CMOV, DL, VT, Ops);
48636 // Fold and/or of setcc's to double CMOV:
48637 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
48638 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
48641 // cmovcc1 (jcc1 if we don't have CMOV)
48647 // cmovne (jne if we don't have CMOV)
48648 // When we can't use the CMOV instruction, it might increase branch
48650 // When we can use CMOV, or when there is no mispredict, this improves
48666 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, VT, LOps);
48669 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, VT, Ops);
48670 return CMOV;
48674 // Fold (CMOV C1, (ADD (CTTZ X), C2), (X != 0)) ->
48675 // (ADD (CMOV C1-C2, (CTTZ X), (X != 0)), C2)
48676 // Or (CMOV (ADD (CTTZ X), C2), C1, (X == 0)) ->
48677 // (ADD (CMOV (CTTZ X), C1-C2, (X == 0)), C2)
48700 DAG.getNode(X86ISD::CMOV, DL, VT, Diff, Add.getOperand(0),
53029 if (StoredVal.getOpcode() == X86ISD::CMOV)
53032 StoredVal.getOperand(0).getOpcode() == X86ISD::CMOV)
54934 if (N0.getOpcode() != X86ISD::CMOV || !N0.hasOneUse())
54958 // We do not want i16 CMOV's. Promote to i32 and truncate afterwards.
54965 SDValue CMov = DAG.getNode(X86ISD::CMOV, DL, CMovVT, CMovOp0, CMovOp1,
55084 // If we face {ANY,SIGN,ZERO}_EXTEND that is applied to a CMOV with constant
55085 // operands and the result of CMOV is not used anywhere else - promote CMOV
55089 // getting rid of result extension code after CMOV will help that.
55090 // 2) Promotion of constant CMOV arguments is free, hence the
55092 // 3) 16-bit CMOV encoding is 4 bytes, 32-bit CMOV is 3-byte, so this
55094 // (64-bit CMOV is 4-bytes, that's why we don't do 32-bit => 64-bit
55098 if (CMovN.getOpcode() != X86ISD::CMOV || !CMovN.hasOneUse())
55131 SDValue Res = DAG.getNode(X86ISD::CMOV, DL, ExtendVT, CMovOp0, CMovOp1,
56409 case X86ISD::CMOV:
56444 case X86ISD::CMOV:
56997 /// CMOV of constants requires materializing constant operands in registers.
56999 /// count. We do this with CMOV rather the generic 'select' because there are
57010 if (V.getOpcode() != X86ISD::CMOV || !V.hasOneUse())
57020 // Match an appropriate CMOV as the first operand of the add.
57054 Cmov = DAG.getNode(X86ISD::CMOV, DL, VT, FalseOp, TrueOp,
57062 return DAG.getNode(X86ISD::CMOV, DL, VT, FalseOp, TrueOp, Cmov.getOperand(2),
57158 if (N1.getOpcode() != X86ISD::CMOV || !N1.hasOneUse())
57181 // Build a new CMOV with the operands swapped.
57182 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VT, TrueOp, FalseOp,
57189 // NEG(ABD(X,Y)) -> NEG(CMOV(SUB(X,Y),SUB(Y,X))) -> CMOV(SUB(Y,X),SUB(X,Y)).
57197 // Build a new CMOV with the operands swapped.
57198 return DAG.getNode(X86ISD::CMOV, DL, VT, TrueOp, FalseOp, N1.getOperand(2),
59357 case X86ISD::CMOV: return combineCMov(N, DAG, DCI, Subtarget);