Lines Matching defs:VirtReg

67   int getStackSpaceFor(Register VirtReg);
69   bool mayLiveOut(Register VirtReg, MachineInstr *CfgMI);
70   void spill(MachineBasicBlock::iterator Before, Register VirtReg, bool Kill);
71   void reload(MachineBasicBlock::iterator UseMI, Register VirtReg,
117 int X86FastPreTileConfig::getStackSpaceFor(Register VirtReg) {
119   int SS = StackSlotForVirtReg[VirtReg];
125   const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
131   StackSlotForVirtReg[VirtReg] = FrameIdx;
135 /// Returns false if \p VirtReg is known to not live out of the current config.
136 /// If \p VirtReg live out of the current MBB, it must live out of the current
138 bool X86FastPreTileConfig::mayLiveOut(Register VirtReg, MachineInstr *CfgMI) {
139   if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg)))
142   for (const MachineInstr &UseInst : MRI->use_nodbg_instructions(VirtReg)) {
144       MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
153         MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
199 /// TODO: Update DBG_VALUEs with \p VirtReg operands with the stack slot.
201                                  Register VirtReg, bool Kill) {
202   LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) << " \n");
203   int FI = getStackSpaceFor(VirtReg);
206   const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
209   TII->storeRegToStackSlot(*MBB, Before, VirtReg, Kill, FI, &RC, TRI,
286 static bool isTileRegister(MachineRegisterInfo *MRI, Register VirtReg) {
287   return getTileDefNum(MRI, VirtReg) > 0;