Lines Matching defs:OpNum

165   unsigned getRegEncoding(const MCInst &MI, unsigned OpNum) const {
166     return MRI.getEncodingValue(MI.getOperand(OpNum).getReg());
189   void setR(const MCInst &MI, unsigned OpNum) {
190     setR(getRegEncoding(MI, OpNum));
192   void setX(const MCInst &MI, unsigned OpNum, unsigned Shift = 3) {
193     MCRegister Reg = MI.getOperand(OpNum).getReg();
200   void setB(const MCInst &MI, unsigned OpNum) {
201     B = getRegEncoding(MI, OpNum) >> 3 & 1;
203   void set4V(const MCInst &MI, unsigned OpNum, bool IsImm = false) {
206       set4V(~(MI.getOperand(OpNum).getImm()));
208       set4V(getRegEncoding(MI, OpNum));
213   void setR2(const MCInst &MI, unsigned OpNum) {
214     setR2(getRegEncoding(MI, OpNum));
216   void setRR2(const MCInst &MI, unsigned OpNum) {
217     unsigned Encoding = getRegEncoding(MI, OpNum);
222   void setXX2(const MCInst &MI, unsigned OpNum) {
223     MCRegister Reg = MI.getOperand(OpNum).getReg();
230   void setBB2(const MCInst &MI, unsigned OpNum) {
231     MCRegister Reg = MI.getOperand(OpNum).getReg();
242   void setV2(const MCInst &MI, unsigned OpNum, bool HasVEX_4V) {
246     MCRegister Reg = MI.getOperand(OpNum).getReg();
251   void set4VV2(const MCInst &MI, unsigned OpNum) {
252     unsigned Encoding = getRegEncoding(MI, OpNum);
256   void setAAA(const MCInst &MI, unsigned OpNum) {
257     EVEX_aaa = getRegEncoding(MI, OpNum);
260   void setSC(const MCInst &MI, unsigned OpNum) {
261     unsigned Encoding = MI.getOperand(OpNum).getImm();
357   unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const;
513                                              unsigned OpNum) const {
514   return Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(OpNum).getReg());