Lines Matching defs:SrcReg

112                           const unsigned SrcReg,
123   bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
126   bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
282   Register SrcReg = I.getOperand(1).getReg();
283   const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
284   const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
293           getRegClass(MRI.getType(SrcReg), SrcRegBank);
303             .addReg(SrcReg)
313   assert((!SrcReg.isPhysical() || I.isCopy()) &&
318           (SrcReg.isPhysical() &&
319            DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
327       SrcReg.isPhysical()) {
330     const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg);
334       I.getOperand(1).substPhysReg(SrcReg, TRI);
338   // No need to constrain SrcReg. It will get constrained when
775     const TargetRegisterClass *DstRC, const unsigned SrcReg,
778   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
796   const Register SrcReg = I.getOperand(1).getReg();
799   const LLT SrcTy = MRI.getType(SrcReg);
802   const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
820     return selectTurnIntoCOPY(I, MRI, DstReg, DstRC, SrcReg, SrcRC);
841   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
860   const Register SrcReg = I.getOperand(1).getReg();
863   const LLT SrcTy = MRI.getType(SrcReg);
893   Register DefReg = SrcReg;
904         .addReg(SrcReg)
925   const Register SrcReg = I.getOperand(1).getReg();
928   const LLT SrcTy = MRI.getType(SrcReg);
931   const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
946     return selectTurnIntoCOPY(I, MRI, SrcReg, SrcRC, DstReg, DstRC);
951   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
967       .addReg(SrcReg)
1229   const Register SrcReg = I.getOperand(1).getReg();
1233   const LLT SrcTy = MRI.getType(SrcReg);
1244     if (!emitExtractSubreg(DstReg, SrcReg, I, MRI, MF))
1279 bool X86InstructionSelector::emitExtractSubreg(unsigned DstReg, unsigned SrcReg,
1284   const LLT SrcTy = MRI.getType(SrcReg);
1301   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1305   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1312       .addReg(SrcReg, 0, SubIdx);
1317 bool X86InstructionSelector::emitInsertSubreg(unsigned DstReg, unsigned SrcReg,
1322   const LLT SrcTy = MRI.getType(SrcReg);
1339   const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1342   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1350       .addReg(SrcReg);
1361   const Register SrcReg = I.getOperand(1).getReg();
1375   if (Index == 0 && MRI.getVRegDef(SrcReg)->isImplicitDef()) {
1420   Register SrcReg = I.getOperand(NumDefs).getReg();
1427              .addReg(SrcReg)