Lines Matching defs:RB
74 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
129 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
171 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const {
172 if (RB.getID() == X86::GPRRegBankID) {
182 if (RB.getID() == X86::VECRRegBankID) {
197 if (RB.getID() == X86::PSRRegBankID) {
261 const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
262 RC = getRegClass(Ty, RB);
449 const RegisterBank &RB,
458 if (X86::GPRRegBankID == RB.getID())
461 if (X86::GPRRegBankID == RB.getID())
464 if (X86::GPRRegBankID == RB.getID())
466 if (X86::VECRRegBankID == RB.getID())
473 if (X86::PSRRegBankID == RB.getID())
476 if (X86::GPRRegBankID == RB.getID())
478 if (X86::VECRRegBankID == RB.getID())
485 if (X86::PSRRegBankID == RB.getID())
569 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
589 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign());