Lines Matching defs:vvvv

878     insn->vvvv =
879         (Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid);
1594 // Consume vvvv from an instruction if it has a VEX prefix.
1598   int vvvv;
1600     vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 |
1603     vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1605     vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1607     vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1612     vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later.
1614   insn->vvvv = static_cast<Reg>(vvvv);
1641   // If non-zero vvvv specified, make sure one of the operands uses it.
1643   needVVVV = hasVVVV && (insn->vvvv != 0);
1654         needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0);
1788         insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7);
1804   // If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail
2431     translateRegister(mcInst, insn.vvvv);