Lines Matching defs:mcInst
1928 /// @param mcInst - The MCInst to append to.
1930 static void translateRegister(MCInst &mcInst, Reg reg) {
1936 mcInst.addOperand(MCOperand::createReg(llvmRegnum));
1951 /// @param mcInst - The MCInst to append to.
1953 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
1965 mcInst.addOperand(baseReg);
1969 mcInst.addOperand(segmentReg);
1975 /// @param mcInst - The MCInst to append to.
1978 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
1990 mcInst.addOperand(baseReg);
1996 /// @param mcInst - The MCInst to append to.
2000 static void translateImmediate(MCInst &mcInst, uint64_t immediate,
2074 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
2077 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
2080 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
2088 mcInst, immediate + pcrel, insn.startLocation, isBranch,
2090 mcInst.addOperand(MCOperand::createImm(immediate));
2095 mcInst.addOperand(segmentReg);
2101 /// @param mcInst - The MCInst to append to.
2105 static bool translateRMRegister(MCInst &mcInst,
2127 mcInst.addOperand(MCOperand::createReg(X86::x)); break;
2139 /// @param mcInst - The MCInst to append to.
2144 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
2286 mcInst.addOperand(baseReg);
2287 mcInst.addOperand(scaleAmount);
2288 mcInst.addOperand(indexReg);
2294 mcInst, insn.displacement + pcrel, insn.startLocation, false,
2296 mcInst.addOperand(displacement);
2297 mcInst.addOperand(segmentReg);
2304 /// @param mcInst - The MCInst to append to.
2309 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
2331 return translateRMRegister(mcInst, insn);
2336 return translateRMMemory(mcInst, insn, Dis);
2338 return translateRMMemory(mcInst, insn, Dis, true);
2345 /// @param mcInst - The MCInst to append to.
2347 static void translateFPRegister(MCInst &mcInst,
2349 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
2355 /// @param mcInst - The MCInst to append to.
2358 static bool translateMaskRegister(MCInst &mcInst,
2365 mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));
2372 /// @param mcInst - The MCInst to append to.
2376 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
2384 translateRegister(mcInst, insn.reg);
2387 return translateMaskRegister(mcInst, insn.writemask);
2391 return translateRM(mcInst, operand, insn, Dis);
2398 translateImmediate(mcInst,
2405 mcInst.addOperand(MCOperand::createImm(insn.RC));
2408 return translateSrcIndex(mcInst, insn);
2410 return translateDstIndex(mcInst, insn);
2416 translateRegister(mcInst, insn.opcodeRegister);
2419 mcInst.addOperand(MCOperand::createImm(insn.immediates[1]));
2423 mcInst.addOperand(MCOperand::createImm(insn.immediates[2]));
2425 mcInst.addOperand(MCOperand::createImm(insn.immediates[1]));
2428 translateFPRegister(mcInst, insn.modRM & 7);
2431 translateRegister(mcInst, insn.vvvv);
2434 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
2442 /// @param mcInst - The MCInst to populate with the instruction's data.
2445 static bool translateInstruction(MCInst &mcInst,
2453 mcInst.clear();
2454 mcInst.setOpcode(insn.instructionID);
2459 if(mcInst.getOpcode() == X86::REP_PREFIX)
2460 mcInst.setOpcode(X86::XRELEASE_PREFIX);
2461 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
2462 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
2469 if (translateOperand(mcInst, Op, insn, Dis)) {