Lines Matching defs:X86
9 // This file is part of the X86 Disassembler.
14 // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and
15 // 64-bit X86 instruction sets. The main decode sequence for an assembly
1816 namespace X86 {
1825 } // namespace X86
1835 /// Generic disassembler for all X86 platforms. All each platform class should
1860 if (FB[X86::Is16Bit]) {
1863 } else if (FB[X86::Is32Bit]) {
1866 } else if (FB[X86::Is64Bit]) {
1901 unsigned Flags = X86::IP_NO_PREFIX;
1903 Flags |= X86::IP_HAS_AD_SIZE;
1906 Flags |= X86::IP_HAS_OP_SIZE;
1908 Flags |= X86::IP_HAS_REPEAT_NE;
1912 Flags |= X86::IP_HAS_REPEAT;
1914 Flags |= X86::IP_HAS_LOCK;
1931 #define ENTRY(x) X86::x,
1941 X86::CS,
1942 X86::SS,
1943 X86::DS,
1944 X86::ES,
1945 X86::FS,
1946 X86::GS
1957 baseRegNo = insn.hasAdSize ? X86::ESI : X86::RSI;
1959 baseRegNo = insn.hasAdSize ? X86::SI : X86::ESI;
1962 baseRegNo = insn.hasAdSize ? X86::ESI : X86::SI;
1982 baseRegNo = insn.hasAdSize ? X86::EDI : X86::RDI;
1984 baseRegNo = insn.hasAdSize ? X86::DI : X86::EDI;
1987 baseRegNo = insn.hasAdSize ? X86::EDI : X86::DI;
2050 // By default sign-extend all X86 immediates based on their encoding.
2074 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
2077 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
2080 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
2127 mcInst.addOperand(MCOperand::createReg(X86::x)); break;
2174 baseReg = MCOperand::createReg(X86::x); break;
2179 baseReg = MCOperand::createReg(X86::NoRegister);
2189 indexReg = MCOperand::createReg(X86::x); break;
2211 indexReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIZ :
2212 X86::RIZ);
2214 indexReg = MCOperand::createReg(X86::NoRegister);
2231 baseReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIP :
2232 X86::RIP);
2235 baseReg = MCOperand::createReg(X86::NoRegister);
2237 indexReg = MCOperand::createReg(X86::NoRegister);
2240 baseReg = MCOperand::createReg(X86::BX);
2241 indexReg = MCOperand::createReg(X86::SI);
2244 baseReg = MCOperand::createReg(X86::BX);
2245 indexReg = MCOperand::createReg(X86::DI);
2248 baseReg = MCOperand::createReg(X86::BP);
2249 indexReg = MCOperand::createReg(X86::SI);
2252 baseReg = MCOperand::createReg(X86::BP);
2253 indexReg = MCOperand::createReg(X86::DI);
2256 indexReg = MCOperand::createReg(X86::NoRegister);
2267 baseReg = MCOperand::createReg(X86::x); break;
2349 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
2365 mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));
2459 if(mcInst.getOpcode() == X86::REP_PREFIX)
2460 mcInst.setOpcode(X86::XRELEASE_PREFIX);
2461 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
2462 mcInst.setOpcode(X86::XACQUIRE_PREFIX);