Lines Matching defs:X86AsmParser

1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
89 class X86AsmParser : public MCTargetAsmParser {
1275   X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
1392 bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
1495 bool X86AsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
1592 bool X86AsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
1597 ParseStatus X86AsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
1609 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1619 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1629 bool X86AsmParser::IsSIReg(MCRegister Reg) {
1643 MCRegister X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, bool IsSIReg) {
1655 void X86AsmParser::AddDefaultSrcDestOperands(
1668 bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1750 bool X86AsmParser::parseOperand(OperandVector &Operands, StringRef Name) {
1757 bool X86AsmParser::CreateMemForMSInlineAsm(
1806 bool X86AsmParser::ParseIntelNamedOperator(StringRef Name,
1848 bool X86AsmParser::ParseMasmNamedOperator(StringRef Name,
1872 void X86AsmParser::tryParseOperandIdx(AsmToken::TokenKind PrevTK,
1880 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
2184 void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
2220 bool X86AsmParser::ParseIntelInlineAsmIdentifier(
2272 bool X86AsmParser::ParseRoundingModeOp(SMLoc Start, OperandVector &Operands) {
2315 bool X86AsmParser::parseCFlagsOp(OperandVector &Operands) {
2375 bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM,
2423 bool X86AsmParser::ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
2444 unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
2458 unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
2489 unsigned X86AsmParser::IdentifyMasmOperator(StringRef Name) {
2503 bool X86AsmParser::ParseMasmOperator(unsigned OpKind, int64_t &Val) {
2554 bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
2580 bool X86AsmParser::parseIntelOperand(OperandVector &Operands, StringRef Name) {
2753 bool X86AsmParser::parseATTOperand(OperandVector &Operands) {
2823 X86::CondCode X86AsmParser::ParseConditionCode(StringRef CC) {
2846 bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
2866 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands) {
2956 bool X86AsmParser::ParseMemOperand(MCRegister SegReg, const MCExpr *Disp,
3172 bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
3188 bool X86AsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
3773 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
3884 bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
3995 void X86AsmParser::emitWarningForSpecialLVIInstruction(SMLoc Loc) {
4013 void X86AsmParser::applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out) {
4058 void X86AsmParser::applyLVILoadHardeningMitigation(MCInst &Inst,
4100 void X86AsmParser::emitInstruction(MCInst &Inst, OperandVector &Operands,
4123 bool X86AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
4168 void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
4194 bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc,
4208 unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4250 bool X86AsmParser::matchAndEmitATTInstruction(
4476 bool X86AsmParser::matchAndEmitIntelInstruction(
4661 bool X86AsmParser::omitRegisterFromClobberLists(MCRegister Reg) {
4665 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
4731 bool X86AsmParser::parseDirectiveArch() {
4739 bool X86AsmParser::parseDirectiveNops(SMLoc L) {
4774 bool X86AsmParser::parseDirectiveEven(SMLoc L) {
4792 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
4830 bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) {
4847 bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) {
4856 bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) {
4865 bool X86AsmParser::parseDirectiveFPOStackAlloc(SMLoc L) {
4874 bool X86AsmParser::parseDirectiveFPOStackAlign(SMLoc L) {
4883 bool X86AsmParser::parseDirectiveFPOEndPrologue(SMLoc L) {
4891 bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
4898 bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
4938 bool X86AsmParser::parseDirectiveSEHPushReg(SMLoc Loc) {
4951 bool X86AsmParser::parseDirectiveSEHSetFrame(SMLoc Loc) {
4971 bool X86AsmParser::parseDirectiveSEHSaveReg(SMLoc Loc) {
4991 bool X86AsmParser::parseDirectiveSEHSaveXMM(SMLoc Loc) {
5011 bool X86AsmParser::parseDirectiveSEHPushFrame(SMLoc Loc) {
5034   RegisterMCAsmParser<X86AsmParser> X(getTheX86_32Target());
5035   RegisterMCAsmParser<X86AsmParser> Y(getTheX86_64Target());