Lines Matching defs:IndexReg
436 MCRegister BaseReg, IndexReg, TmpReg;
472 MCRegister getIndexReg() const { return IndexReg; }
500 // This case mostly happen in inline asm, e.g. Arr[BaseReg + IndexReg]
505 ErrMsg = "BaseReg/IndexReg already set!";
687 // If we already have a BaseReg, then assume this is the IndexReg with
692 if (IndexReg)
694 IndexReg = TmpReg;
746 // If we already have a BaseReg, then assume this is the IndexReg with
751 if (IndexReg)
753 IndexReg = TmpReg;
810 if (IndexReg)
813 IndexReg = Reg;
892 if (IndexReg)
894 IndexReg = TmpReg;
991 // If we already have a BaseReg, then assume this is the IndexReg with
996 if (IndexReg)
998 IndexReg = TmpReg;
1155 MCRegister BaseReg, MCRegister IndexReg,
1304 MCRegister IndexReg, unsigned Scale,
1309 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1320 if (IndexReg &&
1321 !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||
1322 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1323 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1324 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1325 X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
1326 X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
1327 X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {
1332 if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg) ||
1333 IndexReg == X86::EIP || IndexReg == X86::RIP || IndexReg == X86::ESP ||
1334 IndexReg == X86::RSP) {
1349 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
1354 if (BaseReg && IndexReg) {
1356 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1357 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1358 IndexReg == X86::EIZ)) {
1363 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1364 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1365 IndexReg == X86::RIZ)) {
1370 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1371 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
1376 (IndexReg != X86::SI && IndexReg != X86::DI)) {
1615 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1625 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1759 MCRegister IndexReg, unsigned Scale, bool NonAbsMem, SMLoc Start, SMLoc End,
1787 if (BaseReg || IndexReg) {
1790 BaseReg && IndexReg));
1797 getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
2654 MCRegister IndexReg = SM.getIndexReg();
2655 if (IndexReg && BaseReg == X86::RIP)
2662 (IndexReg == X86::ESP || IndexReg == X86::RSP))
2663 std::swap(BaseReg, IndexReg);
2665 // If BaseReg is a vector register and IndexReg is not, swap them unless
2668 !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
2669 X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
2670 X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&
2674 std::swap(BaseReg, IndexReg);
2677 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))
2688 (IndexReg == X86::BX || IndexReg == X86::BP))
2689 std::swap(BaseReg, IndexReg);
2691 if ((BaseReg || IndexReg) &&
2692 CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
2698 return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale,
2710 ((PtrInOperand && !IndexReg) || SM.getElementSize() > 0)) {
2718 } else if (!BaseReg && !IndexReg && Disp &&
2740 if ((BaseReg || IndexReg || RegNo || DefaultBaseReg))
2742 getPointerWidth(), RegNo, Disp, BaseReg, IndexReg, Scale, Start, End,
3043 MCRegister BaseReg, IndexReg;
3082 } else { // IndexReg Found.
3083 IndexReg = cast<X86MCExpr>(E)->getReg();
3088 if (IndexReg == X86::RIP)
3121 if (BaseReg == X86::DX && !IndexReg && Scale == 1 && !SegReg &&
3128 if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
3137 if (BaseReg || IndexReg) {
3141 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg);
3161 if (SegReg || BaseReg || IndexReg)
3163 BaseReg, IndexReg, Scale, StartLoc,
4030 /*BaseReg=*/Basereg, /*IndexReg=*/0,