Lines Matching defs:AVL

165 // Return the AVL operand position for this VVP or VEC Op.
214 bool isLegalAVL(SDValue AVL) { return AVL->getOpcode() == VEISD::LEGALAVL; }
396 SDValue AVL = getNodeAVL(Op);
397 if (!AVL)
399 if (isLegalAVL(AVL))
400 return {AVL->getOperand(0), true};
401 return {AVL, false};
414 auto AVL = getConstant(MaskVT.getVectorNumElements(), MVT::i32);
415 auto Res = getNode(VEISD::VEC_BROADCAST, MaskVT, {TrueVal, AVL});
423 SDValue AVL) const {
440 DAG.getNode(VEISD::VEC_BROADCAST, DL, CmpVecTy, {CmpElem, AVL});
442 getBroadcast(CmpVecTy, {DAG.getConstant(0, DL, ScalarBoolVT)}, AVL);
452 SDValue AVL) const {
457 return getMaskBroadcast(ResultVT, Scalar, AVL);
471 return getNode(VEISD::VEC_BROADCAST, ResultVT, {Scalar, AVL});
474 SDValue VECustomDAG::annotateLegalAVL(SDValue AVL) const {
475 if (isLegalAVL(AVL))
476 return AVL;
477 return getNode(VEISD::LEGALAVL, AVL.getValueType(), AVL);
481 SDValue AVL) const {
482 assert(getAnnotatedNodeAVL(AVL).second && "Expected a pack-legalized AVL");
487 return DAG.getNode(OC, DL, DestVT, Vec, AVL);
491 SDValue AVL) const {
492 assert(getAnnotatedNodeAVL(AVL).second && "Expected a pack-legalized AVL");
495 return DAG.getNode(VEISD::VEC_PACK, DL, DestVT, LoVec, HiVec, AVL);
500 // Adjust AVL for this part
538 SDValue AVL) const {
546 SDValue ScaleBroadcast = getBroadcast(IndexVT, Scale, AVL);
548 getNode(VEISD::VVP_MUL, IndexVT, {Index, ScaleBroadcast, Mask, AVL});
556 SDValue BaseBroadcast = getBroadcast(IndexVT, BasePtr, AVL);
558 getNode(VEISD::VVP_ADD, IndexVT, {BaseBroadcast, ScaledIndex, Mask, AVL});
564 SDValue Mask, SDValue AVL,
583 getNode(VVPOpcode, ResVT, {StartV, VectorV, Mask, AVL}, Flags));
586 getNode(VVPOpcode, ResVT, {VectorV, Mask, AVL}, Flags));