Lines Matching defs:Outs

237     const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
241   return CCInfo.CheckReturn(Outs, Subtarget->is64Bit() ? RetCC_Sparc64
248                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
252     return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
253   return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
259                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
272   CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
344                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
355   CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
792   auto &Outs = CLI.Outs;
808   if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
813   for (auto &Arg : Outs)
826   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
840   CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
855   for (unsigned i = 0,  e = Outs.size(); i != e; ++i) {
856     ISD::ArgFlagsTy Flags = Outs[i].Flags;
900     ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
942       assert(Outs[realArgIdx].OrigArgIndex == 0);
1181                                    ArrayRef<ISD::OutputArg> Outs) {
1189     if (Outs[VA.getValNo()].IsFixed)
1235   CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1252     fixupVariableFloatArgs(ArgLocs, CLI.Outs);