Lines Matching defs:MIB
101 MachineIRBuilder MIB(MF);
103 GR->getOrCreateSPIRVType(Const->getType(), MIB);
177 static void buildOpBitcast(SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB,
184 MachineRegisterInfo *MRI = MIB.getMRI();
188 MIB.buildInstr(TargetOpcode::COPY).addDef(ResVReg).addUse(OpReg);
190 MIB.buildInstr(SPIRV::OpBitcast)
196 // We do instruction selections early instead of calling MIB.buildBitcast()
215 MachineIRBuilder MIB) {
221 MIB.setInsertPt(*MI.getParent(), MI);
222 buildOpBitcast(GR, MIB, MI.getOperand(0).getReg(),
232 MachineIRBuilder MIB) {
235 static_cast<const SPIRVSubtarget *>(&MIB.getMF().getSubtarget());
243 MIB.setInsertPt(*MI.getParent(), MI);
246 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg());
252 SPIRVType *BaseTy = GR->getOrCreateSPIRVType(ElemTy, MIB);
259 MachineRegisterInfo *MRI = MIB.getMRI();
267 MIB.buildBitcast(Def, Source);
291 MachineIRBuilder &MIB) {
301 MIB.setInsertPt(*MI->getParent(), MI);
303 SpvType = GR->getOrCreateSPIRVType(Ty, MIB);
307 MIB.setInsertPt(*MI->getParent(), MI);
312 SpvType = GR->getOrCreateSPIRVType(Ty, MIB);
321 if (SPIRVType *Def = propagateSPIRVType(DefInstr, GR, MRI, MIB)) {
326 SpvType = GR->getOrCreateSPIRVIntegerType(ExpectedBW, MIB);
329 GR->getOrCreateSPIRVVectorType(SpvType, NumElements, MIB);
337 MRI.getType(Reg).getScalarSizeInBits(), MIB);
346 SpvType = propagateSPIRVType(Def, GR, MRI, MIB);
365 GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
412 static void setInsertPtAfterDef(MachineIRBuilder &MIB, MachineInstr *Def) {
420 MIB.setInsertPt(MBB, DefIt);
430 SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB,
434 setInsertPtAfterDef(MIB, Def);
435 SpvType = SpvType ? SpvType : GR->getOrCreateSPIRVType(Ty, MIB);
444 GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
447 GR->assignSPIRVTypeToVReg(SpvType, NewReg, MIB.getMF());
451 MIB.buildInstr(SPIRV::ASSIGN_TYPE)
466 void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
468 MIB.setInsertPt(*MI.getParent(), MI.getIterator());
475 MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(OpReg);
486 MachineIRBuilder MIB,
490 static_cast<const SPIRVSubtarget *>(&MIB.getMF().getSubtarget());
520 MIB.setInsertPt(*MI.getParent(), MI.getIterator());
522 SPIRVType *BaseTy = GR->getOrCreateSPIRVType(ElementTy, MIB);
531 insertAssignInstr(Reg, nullptr, AssignedPtrType, GR, MIB,
542 insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MF.getRegInfo());
636 insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MRI);
638 propagateSPIRVType(&MI, GR, MRI, MIB);
666 propagateSPIRVType(&MI, GR, MRI, MIB);
678 MachineIRBuilder MIB) {
683 processInstr(MI, MIB, MRI, GR);
813 static void insertSpirvDecorations(MachineFunction &MF, MachineIRBuilder MIB) {
819 MIB.setInsertPt(*MI.getParent(), MI.getNextNode());
820 buildOpSpirvDecorations(MI.getOperand(1).getReg(), MIB,
834 MachineIRBuilder MIB) {
882 MachineIRBuilder MIB) {
1002 MachineIRBuilder MIB) {
1011 MIB.setInsertPt(MBB, MBB.end());
1012 MIB.buildBr(**MBB.successors().begin());
1021 MachineIRBuilder MIB(MF);
1028 insertBitcasts(MF, GR, MIB);
1029 generateAssignInstrs(MF, GR, MIB, TargetExtConstTypes);
1031 processSwitchesConstants(MF, GR, MIB);
1032 processBlockAddr(MF, GR, MIB);
1035 processInstrsWithTypeFolding(MF, GR, MIB);
1036 removeImplicitFallthroughs(MF, MIB);
1037 insertSpirvDecorations(MF, MIB);
1038 insertInlineAsm(MF, GR, ST, MIB);
1039 selectOpBitcasts(MF, GR, MIB);