Lines Matching defs:BitWidth

46 SPIRVType *SPIRVGlobalRegistry::assignIntTypeToVReg(unsigned BitWidth,
50   SPIRVType *SpirvType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
56 SPIRVGlobalRegistry::assignFloatTypeToVReg(unsigned BitWidth, Register VReg,
59   SPIRVType *SpirvType = getOrCreateSPIRVFloatType(BitWidth, I, TII);
237   unsigned BitWidth = getScalarOrVectorBitWidth(SpvType);
244         CurMF->getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
249       assignIntTypeToVReg(BitWidth, Res, *I, *TII);
253   return std::make_tuple(Res, CI, NewInstr, BitWidth);
264   unsigned BitWidth = getScalarOrVectorBitWidth(SpvType);
271         CurMF->getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
276       assignFloatTypeToVReg(BitWidth, Res, *I, *TII);
280   return std::make_tuple(Res, CI, NewInstr, BitWidth);
291   unsigned BitWidth;
292   std::tie(Res, CI, New, BitWidth) =
311           APInt(BitWidth, CI->getValueAPF().bitcastToAPInt().getZExtValue()),
330   unsigned BitWidth;
331   std::tie(Res, CI, New, BitWidth) =
345       addNumImm(APInt(BitWidth, Val), MIB);
372     unsigned BitWidth = getScalarOrVectorBitWidth(SpvType);
373     LLT LLTy = LLT::scalar(BitWidth);
389           addNumImm(APInt(BitWidth, Val), MIB);
439     const SPIRVInstrInfo &TII, unsigned BitWidth, bool ZeroAsNull) {
447     SPIRVType *SpvBaseType = getOrCreateSPIRVFloatType(BitWidth, I, TII);
452   SPIRVType *SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
459     const SPIRVInstrInfo &TII, Constant *CA, unsigned BitWidth,
472           getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth, ZeroAsNull);
570     Constant *CA, unsigned BitWidth, unsigned ElemCnt) {
576           getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder);
579     LLT LLTy = EmitIR ? LLT::fixed_vector(ElemCnt, BitWidth) : LLT::scalar(64);
988       unsigned BitWidth = adjustOpTypeIntWidth(SrcBitWidth);
990       if (SrcBitWidth != BitWidth)
991         Ty = IntegerType::get(Ty->getContext(), BitWidth);
1466 SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType(unsigned BitWidth,
1469       IntegerType::get(MIRBuilder.getMF().getFunction().getContext(), BitWidth),
1481 SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVType(unsigned BitWidth,
1492                  .addImm(BitWidth)
1499     unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) {
1504   BitWidth = adjustOpTypeIntWidth(BitWidth);
1505   Type *LLVMTy = IntegerType::get(CurMF->getFunction().getContext(), BitWidth);
1506   return getOrCreateSPIRVType(BitWidth, I, TII, SPIRV::OpTypeInt, LLVMTy);
1510     unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) {
1513   switch (BitWidth) {
1526   return getOrCreateSPIRVType(BitWidth, I, TII, SPIRV::OpTypeFloat, LLVMTy);