Lines Matching defs:ISD

1057     return ISD::VPSD;
1061 return ISD::DELETED_NODE;
1084 if (!LT.second.isVector() && TLI->isOperationCustom(ISD::FCEIL, LT.second))
1180 FsqrtType = TLI->getTypeToPromoteTo(ISD::FSQRT, FsqrtType);
1193 FsqrtType = TLI->getTypeToPromoteTo(ISD::FSQRT, FsqrtType);
1286 if (TLI->isOperationCustom(ISD::VP_FRINT, LT.second))
1294 if (TLI->isOperationCustom(ISD::VP_FRINT, LT.second))
1371 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1372 assert(ISD && "Invalid opcode");
1381 switch (ISD) {
1384 case ISD::SIGN_EXTEND:
1385 case ISD::ZERO_EXTEND:
1397 case ISD::TRUNCATE:
1429 switch (ISD) {
1430 case ISD::SIGN_EXTEND:
1431 case ISD::ZERO_EXTEND: {
1437 (ISD == ISD::SIGN_EXTEND) ? SExtOp[PowDiff - 1] : ZExtOp[PowDiff - 1];
1440 case ISD::TRUNCATE:
1441 case ISD::FP_EXTEND:
1442 case ISD::FP_ROUND: {
1447 unsigned Op = (ISD == ISD::TRUNCATE) ? RISCV::VNSRL_WI
1448 : (ISD == ISD::FP_EXTEND) ? RISCV::VFWCVT_F_F_V
1452 MVT ElementMVT = (ISD == ISD::TRUNCATE)
1462 case ISD::FP_TO_SINT:
1463 case ISD::FP_TO_UINT: {
1464 unsigned IsSigned = ISD == ISD::FP_TO_SINT;
1506 case ISD::SINT_TO_FP:
1507 case ISD::UINT_TO_FP: {
1508 unsigned IsSigned = ISD == ISD::SINT_TO_FP;
1677 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1678 assert(ISD && "Invalid opcode");
1680 if (ISD != ISD::ADD && ISD != ISD::OR && ISD != ISD::XOR && ISD != ISD::AND &&
1681 ISD != ISD::FADD)
1695 if (ISD == ISD::AND) {
1715 } else if (ISD == ISD::XOR || ISD == ISD::ADD) {
1725 assert(ISD == ISD::OR);
1744 switch (ISD) {
1745 case ISD::ADD:
1749 case ISD::OR:
1753 case ISD::XOR:
1757 case ISD::AND:
1761 case ISD::FADD:
2274 case ISD::ADD:
2275 case ISD::SUB:
2278 case ISD::SHL:
2279 case ISD::SRL:
2280 case ISD::SRA:
2283 case ISD::AND:
2284 case ISD::OR:
2285 case ISD::XOR:
2288 case ISD::MUL:
2289 case ISD::MULHS:
2290 case ISD::MULHU:
2293 case ISD::SDIV:
2294 case ISD::UDIV:
2297 case ISD::SREM:
2298 case ISD::UREM:
2301 case ISD::FADD:
2302 case ISD::FSUB:
2305 case ISD::FMUL:
2308 case ISD::FDIV:
2311 case ISD::FNEG: