Lines Matching full:sequence
240 // The order of registers represents the preferred allocation sequence.
242 def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17),
243 (sequence "X%u", 5, 7),
244 (sequence "X%u", 28, 31),
245 (sequence "X%u", 8, 9),
246 (sequence "X%u", 18, 27),
247 (sequence "X%u", 0, 4))>;
263 def GPRJALR : GPRRegisterClass<(sub GPR, (sequence "X%u", 0, 5))>;
267 def GPRC : GPRRegisterClass<(add (sequence "X%u", 10, 15),
268 (sequence "X%u", 8, 9))>;
274 def GPRTC : GPRRegisterClass<(add (sequence "X%u", 6, 7),
275 (sequence "X%u", 10, 17),
276 (sequence "X%u", 28, 31))>;
282 def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
283 (sequence "X%u", 18, 23))>;
394 // The order of registers represents the preferred allocation sequence,
399 (sequence "F%u_H", 15, 10), // fa5-fa0
400 (sequence "F%u_H", 0, 7), // ft0-f7
401 (sequence "F%u_H", 16, 17), // fa6-fa7
402 (sequence "F%u_H", 28, 31), // ft8-ft11
403 (sequence "F%u_H", 8, 9), // fs0-fs1
404 (sequence "F%u_H", 18, 27) // fs2-fs11
408 (sequence "F%u_H", 15, 10),
409 (sequence "F%u_H", 8, 9)
413 (sequence "F%u_F", 15, 10),
414 (sequence "F%u_F", 0, 7),
415 (sequence "F%u_F", 16, 17),
416 (sequence "F%u_F", 28, 31),
417 (sequence "F%u_F", 8, 9),
418 (sequence "F%u_F", 18, 27)
422 (sequence "F%u_F", 15, 10),
423 (sequence "F%u_F", 8, 9)
426 // The order of registers represents the preferred allocation sequence,
429 (sequence "F%u_D", 15, 10),
430 (sequence "F%u_D", 0, 7),
431 (sequence "F%u_D", 16, 17),
432 (sequence "F%u_D", 28, 31),
433 (sequence "F%u_D", 8, 9),
434 (sequence "F%u_D", 18, 27)
438 (sequence "F%u_D", 15, 10),
439 (sequence "F%u_D", 8, 9)
447 def GPRF16 : RISCVRegisterClass<[f16], 16, (add (sequence "X%u_H", 10, 17),
448 (sequence "X%u_H", 5, 7),
449 (sequence "X%u_H", 28, 31),
450 (sequence "X%u_H", 8, 9),
451 (sequence "X%u_H", 18, 27),
452 (sequence "X%u_H", 0, 4))>;
453 def GPRF16C : RISCVRegisterClass<[f16], 16, (add (sequence "X%u_H", 10, 15),
454 (sequence "X%u_H", 8, 9))>;
457 def GPRF32 : RISCVRegisterClass<[f32], 32, (add (sequence "X%u_W", 10, 17),
458 (sequence "X%u_W", 5, 7),
459 (sequence "X%u_W", 28, 31),
460 (sequence "X%u_W", 8, 9),
461 (sequence "X%u_W", 18, 27),
462 (sequence "X%u_W", 0, 4))>;
463 def GPRF32C : RISCVRegisterClass<[f32], 32, (add (sequence "X%u_W", 10, 15),
464 (sequence "X%u_W", 8, 9))>;
730 (add (sequence "V%u", 8, 31),
731 (sequence "V%u", 7, 0)), 1>;
735 def VRM2 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2),
736 (sequence "V%uM2", 6, 0, 2)), 2>;