Lines Matching defs:OffsetTail

175 // OffsetTail: addi  voff, vreg3, 188                OffsetTail: lui  voff, 128
194   MachineInstr &OffsetTail = *MRI->getVRegDef(Reg);
195   if (OffsetTail.getOpcode() == RISCV::ADDI ||
196       OffsetTail.getOpcode() == RISCV::ADDIW) {
199     MachineOperand &AddiImmOp = OffsetTail.getOperand(2);
202     Register AddiReg = OffsetTail.getOperand(1).getReg();
207       LLVM_DEBUG(dbgs() << "  Offset Instrs: " << OffsetTail);
209       OffsetTail.eraseFromParent();
222     if (!ST->is64Bit() || OffsetTail.getOpcode() == RISCV::ADDIW)
227     LLVM_DEBUG(dbgs() << "  Offset Instrs: " << OffsetTail
230     OffsetTail.eraseFromParent();
233   } else if (OffsetTail.getOpcode() == RISCV::LUI) {
236     LLVM_DEBUG(dbgs() << "  Offset Instr: " << OffsetTail);
237     int64_t Offset = SignExtend64<32>(OffsetTail.getOperand(1).getImm() << 12);
239     OffsetTail.eraseFromParent();
254 // OffsetTail: addi    voff, x0, C
275   MachineInstr &OffsetTail = *MRI->getVRegDef(Rs1);
276   if (OffsetTail.getOpcode() != RISCV::ADDI)
278   if (!OffsetTail.getOperand(1).isReg() ||
279       OffsetTail.getOperand(1).getReg() != RISCV::X0 ||
280       !OffsetTail.getOperand(2).isImm())
283   int64_t Offset = OffsetTail.getOperand(2).getImm();
296   LLVM_DEBUG(dbgs() << "  Offset Instr: " << OffsetTail);
298   OffsetTail.eraseFromParent();