Lines Matching defs:RegImm

296                                         RegImmPair RegImm,
310     if (CandidateRegImm.Reg == RegImm.Reg && CandidateRegImm.Imm == RegImm.Imm)
313     // If RegImm.Reg is modified by this instruction, then we cannot optimize
318     if (MI.modifiesRegister(RegImm.Reg, TRI))
327   if (MIs.size() < 2 || (RegImm.Imm != 0 && MIs.size() < 3))
335   if (RISCV::GPRRegClass.contains(RegImm.Reg))
337   else if (RISCV::GPRF16RegClass.contains(RegImm.Reg))
339   else if (RISCV::GPRF32RegClass.contains(RegImm.Reg))
341   else if (RISCV::FPR32RegClass.contains(RegImm.Reg))
343   else if (RISCV::FPR64RegClass.contains(RegImm.Reg))
413       RegImmPair RegImm = getRegImmPairPreventingCompression(MI);
414       if (!RegImm.Reg && RegImm.Imm == 0)
421       Register NewReg = analyzeCompressibleUses(MI, RegImm, MIs);
426       if (RISCV::GPRRegClass.contains(RegImm.Reg)) {
427         assert(isInt<12>(RegImm.Imm));
429             .addReg(RegImm.Reg)
430             .addImm(RegImm.Imm);
431       } else if (RISCV::GPRF16RegClass.contains(RegImm.Reg)) {
432         assert(RegImm.Imm == 0);
435             .addReg(RegImm.Reg);
436       } else if (RISCV::GPRF32RegClass.contains(RegImm.Reg)) {
437         assert(RegImm.Imm == 0);
440             .addReg(RegImm.Reg);
446         assert(RegImm.Imm == 0);
447         unsigned Opcode = RISCV::FPR32RegClass.contains(RegImm.Reg)
451             .addReg(RegImm.Reg)
452             .addReg(RegImm.Reg);
458       // TODO: Update all uses if RegImm.Imm == 0? Not just those that are
461         updateOperands(*UpdateMI, RegImm, NewReg);