Lines Matching defs:MBB
217 bool computeVXRMChanges(const MachineBasicBlock &MBB);
218 void computeAvailable(const MachineBasicBlock &MBB);
219 void computeAnticipated(const MachineFunction &MF, const MachineBasicBlock &MBB);
220 void emitWriteVXRM(MachineBasicBlock &MBB);
240 bool RISCVInsertWriteVXRM::computeVXRMChanges(const MachineBasicBlock &MBB) {
241 BlockData &BBInfo = BlockInfo[MBB.getNumber()];
244 for (const MachineInstr &MI : MBB) {
269 void RISCVInsertWriteVXRM::computeAvailable(const MachineBasicBlock &MBB) {
270 BlockData &BBInfo = BlockInfo[MBB.getNumber()];
275 if (MBB.pred_empty()) {
278 for (const MachineBasicBlock *P : MBB.predecessors())
288 LLVM_DEBUG(dbgs() << "AvailableIn state of " << printMBBReference(MBB)
299 LLVM_DEBUG(dbgs() << "AvailableOut state of " << printMBBReference(MBB)
303 for (MachineBasicBlock *S : MBB.successors()) {
311 void RISCVInsertWriteVXRM::computeAnticipated(const MachineFunction &MF, const MachineBasicBlock &MBB) {
312 BlockData &BBInfo = BlockInfo[MBB.getNumber()];
318 if (MBB.succ_empty()) {
321 for (const MachineBasicBlock *S : MBB.successors())
336 LLVM_DEBUG(dbgs() << "AnticipatedOut state of " << printMBBReference(MBB)
348 LLVM_DEBUG(dbgs() << "AnticipatedIn state of " << printMBBReference(MBB)
352 for (MachineBasicBlock *P : MBB.predecessors()) {
360 void RISCVInsertWriteVXRM::emitWriteVXRM(MachineBasicBlock &MBB) {
361 const BlockData &BBInfo = BlockInfo[MBB.getNumber()];
372 if (MBB.isEntryBlock()) {
380 for (MachineBasicBlock *P : MBB.predecessors()) {
402 for (MachineInstr &MI : MBB) {
413 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteVXRMImm))
442 LLVM_DEBUG(dbgs() << "Inserting at end of " << printMBBReference(MBB)
444 BuildMI(MBB, MBB.getFirstTerminator(), DebugLoc(),
463 for (const MachineBasicBlock &MBB : MF)
464 NeedVXRMChange |= computeVXRMChanges(MBB);
472 for (const MachineBasicBlock &MBB : MF) {
473 WorkList.push(&MBB);
474 BlockInfo[MBB.getNumber()].InQueue = true;
477 const MachineBasicBlock &MBB = *WorkList.front();
479 computeAvailable(MBB);
483 for (const MachineBasicBlock &MBB : llvm::reverse(MF)) {
484 WorkList.push(&MBB);
485 BlockInfo[MBB.getNumber()].InQueue = true;
488 const MachineBasicBlock &MBB = *WorkList.front();
490 computeAnticipated(MF, MBB);
494 for (MachineBasicBlock &MBB : MF)
495 emitWriteVXRM(MBB);