Lines Matching defs:SEW
141 /// not a load or store which ignores SEW.
219 // What properties of SEW we need to preserve.
221 SEWEqual = 3, // The exact value of SEW needs to be preserved.
223 2, // SEW can be changed as long as it's greater
226 SEWGreaterThanOrEqual = 1, // SEW can be changed as long as it's greater
228 SEWNone = 0 // We don't need to preserve SEW at all.
229 } SEW = SEWNone;
244 return SEW || LMUL || SEWLMULRatio || TailPolicy || MaskPolicy || VILL;
254 SEW = SEWEqual;
279 SEW = std::max(SEW, B.SEW);
299 OS << "SEW=";
300 switch (SEW) {
355 switch (Used.SEW) {
407 // SEW, VL, or Policy operand even though it might not be the exact value in
434 // Loads and stores with implicit EEW do not demand SEW or LMUL directly.
436 // EMUL, but which allows us the flexibility to change SEW and LMUL
438 // Note: We assume that the instructions initial SEW is the EEW encoded
441 Res.SEW = DemandedFields::SEWNone;
456 Res.SEW = DemandedFields::SEWNone;
473 Res.SEW = DemandedFields::SEWGreaterThanOrEqualAndLessThan64;
475 Res.SEW = DemandedFields::SEWGreaterThanOrEqual;
480 // vmv.x.s, and vfmv.f.s are unconditional and ignore everything except SEW.
494 // * We can't modify SEW here since the slide amount is in units of SEW.
519 Res.SEW = DemandedFields::SEWGreaterThanOrEqualAndLessThan64;
521 Res.SEW = DemandedFields::SEWGreaterThanOrEqual;
526 // In ยง32.16.6, whole vector register moves have a dependency on SEW. At the
528 // result whatever the SEW may be.
530 // However it does need valid SEW, i.e. vill must be cleared. The entry to a
535 Res.SEW = DemandedFields::SEWNone;
568 uint8_t SEW = 0;
644 unsigned getSEW() const { return SEW; }
706 SEW = RISCVVType::getSEW(VType);
714 SEW = S;
724 return RISCVVType::encodeVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic);
735 "Can't compare when only LMUL/SEW ratio is valid.");
736 return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) ==
737 std::tie(Other.VLMul, Other.SEW, Other.TailAgnostic,
744 return RISCVVType::getSEWLMULRatio(SEW, VLMul);
840 // return an SEW/LMUL ratio only value.
874 << "SEW=" << (unsigned)SEW << ", "
973 // %vl = PseudoVSETVLI %avl:gpr, SEW=32, LMUL=M1
974 // $x0 = PseudoVSETVLI %vl:gpr, SEW=32, LMUL=M1
976 // %vl = PseudoVSETVLI %avl:gpr, SEW=32, LMUL=M1
977 // $x0 = PseudoVSETVLI %avl:gpr, SEW=32, LMUL=M1
1020 static unsigned computeVLMAX(unsigned VLEN, unsigned SEW,
1027 return VLEN/SEW;
1065 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
1066 assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");
1076 const unsigned VLMAX = computeVLMAX(ST->getRealMaxVLen(), SEW, VLMul);
1099 assert(SEW == EEW && "Initial SEW doesn't match expected EEW");
1102 InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic);
1115 // Use X0, X0 form if the AVL is the same and the SEW+LMUL gives the same
1223 // If we don't use LMUL or the SEW/LMUL ratio, then adjust LMUL so that we
1224 // maintain the SEW/LMUL ratio. This allows us to eliminate VL toggles in more
1290 ((Demanded.SEW || Demanded.SEWLMULRatio) ? IncomingInfo : Info).getSEW(),