Lines Matching defs:XOR

1236                               ISD::OR, ISD::XOR},
1270                             ISD::XOR, ISD::SDIV, ISD::SREM, ISD::UDIV,
1508                        ISD::AND, ISD::OR, ISD::XOR, ISD::SETCC, ISD::SELECT});
6290   unsigned LogicOpc = IsFABS ? ISD::AND : ISD::XOR;
6463   case ISD::XOR:
7488   case ISD::XOR:
8237       return DAG.getNode(ISD::XOR, DL, VT, Neg, FalseV);
8432       SDValue XOR = DAG.getNode(ISD::XOR, DL, XLenVT, CondV,
8434       return DAG.getNode(ISD::SINT_TO_FP, DL, VT, XOR);
10269       Vec = DAG.getNode(ISD::XOR, DL, ContainerVT, Vec, TrueMask);
10302   // AND gives us (0 == 0) -> 1 and OR/XOR give us (0 != 0) -> 0. Therefore we
13199         DAG.getNode(ISD::XOR, DL, OType, ConditionRHS, ResultLowerThanLHS);
13286     SDValue NewRes = DAG.getNode(ISD::XOR, DL, MVT::i64, Src, SignFill);
13623   case ISD::XOR:
13753     case ISD::XOR:
14102   if (N0.getOpcode() != ISD::XOR || !isOneConstant(N0.getOperand(1)))
14167   } else if (N1.getOpcode() == ISD::XOR && isOneConstant(N1.getOperand(1)) &&
14274   if (N0.getOpcode() != ISD::XOR || N1.getOpcode() != ISD::XOR)
14310   return DAG.getNode(ISD::XOR, DL, VT, Logic, DAG.getConstant(1, DL, VT));
14466   if (TrueV.getOpcode() != ISD::XOR || FalseV.getOpcode() != ISD::XOR ||
14480   return DAG.getNode(ISD::XOR, DL, VT, NewOr, TrueV.getOperand(1));
16603       Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse())
16684   if (LHS.getOpcode() == ISD::XOR && isNullConstant(RHS)) {
16756   case ISD::XOR:
17736       SDValue NewHi = DAG.getNode(ISD::XOR, DL, MVT::i32, Hi,
17819       return DAG.getNode(ISD::XOR, DL, VT, NewFMV,
17858   case ISD::XOR:
17955     if (Cond.getOpcode() == ISD::XOR && isOneConstant(Cond.getOperand(1))) {
18065     if (TrueV.getOpcode() == ISD::XOR && FalseV.getOpcode() == ISD::XOR &&
18071       return DAG.getNode(ISD::XOR, DL, VT, NewSel, TrueV.getOperand(1));
18796   if (Opcode != ISD::AND && Opcode != ISD::OR && Opcode != ISD::XOR)