Lines Matching defs:XLen
363 // With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll
9500 // We need to special case these when the scalar is larger than XLen.
13045 unsigned XLen = Subtarget.getXLen();
13047 if (Size > XLen) {
13048 assert(Size == (XLen * 2) && "Unexpected custom legalisation");
13051 APInt HighMask = APInt::getHighBitsSet(Size, XLen);
13068 bool LHSIsS = DAG.ComputeNumSignBits(LHS) > XLen;
13069 bool RHSIsS = DAG.ComputeNumSignBits(RHS) > XLen;
13507 // Extend inputs to XLen, and shift by 32. This will add 64 trailing zeros
13914 // Maybe harmful when VT is wider than XLen.
16152 // Only handle XLen or i32 types. Other types narrower than XLen will
16182 // Only handle XLen types. Other types narrower than XLen will eventually be
16487 // (sra (shl X, C1+(XLen-iX)), C2+(XLen-iX)) so it gets selected as SLLI+SRAI.
16690 // Fold ((srl (and X, 1<<C), C), 0, eq/ne) -> ((shl X, XLen-1-C), 0, ge/lt)
18397 // any power-of-two size up to XLen bits, provided that they aren't too
19077 // element type is wider than XLen, the least-significant XLEN bits are
19079 unsigned XLen = Subtarget.getXLen();
19081 if (EltBits <= XLen)
19082 return XLen - EltBits + 1;
21184 // TODO: Support fixed vectors up to XLen for P extension?
21563 getIntrinsicForMaskedAtomicRMWBinOp(unsigned XLen, AtomicRMWInst::BinOp BinOp) {
21564 if (XLen == 32) {
21587 if (XLen == 64) {
21610 llvm_unreachable("Unexpected XLen\n");
21632 unsigned XLen = Subtarget.getXLen();
21634 Builder.getIntN(XLen, static_cast<uint64_t>(AI->getOrdering()));
21638 getIntrinsicForMaskedAtomicRMWBinOp(XLen, AI->getOperation()), Tys);
21640 if (XLen == 64) {
21650 // bits to shift the value into position. Pass XLen-ShiftAmt-ValWidth, which
21659 Builder.CreateSub(Builder.getIntN(XLen, XLen - ValWidth), ShiftAmt);
21667 if (XLen == 64)
21689 unsigned XLen = Subtarget.getXLen();
21690 Value *Ordering = Builder.getIntN(XLen, static_cast<uint64_t>(Ord));
21692 if (XLen == 64) {
21701 if (XLen == 64)
21930 // size exceeds XLen.
22822 // Some integer types smaller than XLen are listed in the GPR register class to