Lines Matching defs:SRA

317     setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL, ISD::SRA, ISD::SRL},
1271                             ISD::UREM, ISD::SHL, ISD::SRA, ISD::SRL},
1509   setTargetDAGCombine(ISD::SRA);
1531                          ISD::VP_SCATTER,    ISD::SRA,
1967       (Val.getOpcode() == ISD::SRL || Val.getOpcode() == ISD::SRA) &&
4357   // Detect cases where Hi is (SRA Lo, 31) which means Hi is Lo sign extended.
4358   if (Hi.getOpcode() == ISD::SRA && Hi.getOperand(0) == Lo &&
6378   OP_CASE(SRA)
7497   case ISD::SRA:
8648   // SRA expansion:
8664   unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
8681       IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, XLenMinus1) : Zero;
12853   case ISD::SRA:
13089   case ISD::SRA:
13283     SignFill = DAG.getNode(ISD::SRA, DL, MVT::i64, SignFill,
14251       return DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0),
14776   SDValue Sra = DAG.getNode(ISD::SRA, DL, HalfVT, Cast,
16473   assert(N->getOpcode() == ISD::SRA && "Unexpected opcode");
16502         return DAG.getNode(ISD::SRA, DL, VT, Shl,
16520   // We might have an ADD or SUB between the SRA and SHL.
16536       if (U->getOpcode() != ISD::SRA ||
16656       LHS.getOpcode() == ISD::SRA) {
16749   case ISD::SRA:
17477   if (Op.getOpcode() != ISD::SRA || !Op.hasOneUse())
17497   return DAG.getNode(ISD::SRA, SDLoc(N), N->getValueType(0), N00, SMin);
18002         SDValue SRA =
18003             DAG.getNode(ISD::SRA, DL, VT, LHS,
18006             DAG.getNode(ISD::AND, DL, VT, SRA,
18325   case ISD::SRA:
18698   assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||