Lines Matching defs:SEW

2694     // each fractional LMUL we support SEW between 8 and LMUL*ELEN.
3411 // in, i.e. SEW for build_vectors or XLEN for address calculations.
4948   // twice the SEW (Hence the restriction on not using the maximum
5418         // If this is SEW=64 on RV32, use a strided load with a stride of x0.
5607     // to a wider SEW.
5721   // to a wider SEW.
8716 // Custom-lower a SPLAT_VECTOR_PARTS where XLEN<SEW, as the SEW element type is
8884   // RVV only has truncates which operate from SEW*2->SEW, so lower arbitrary
9478   // that a widening operation never uses SEW=64.
9489   // instruction to sign-extend since SEW>XLEN.
9511     // Double the VL since we halved SEW.
9536       SDValue SEW = DAG.getConstant(Sew, DL, XLenVT);
9542                                SEW, LMUL);
9549     // Shift the two scalar parts in using SEW=32 slide1up/slide1down
9606 // SEW=8 for the vsetvli because it is the only element width that supports all
9607 // fractional LMULs. The LMUL is choosen so that with SEW=8 the VLMax is
9610 // SEW and LMUL are better for the surrounding vector instructions.
9727 // LMUL * VLEN should be greater than or equal to EGS * SEW
9902       report_fatal_error("EGW should be greater than or equal to 4 * SEW.");
9910       report_fatal_error("EGW should be greater than or equal to 8 * SEW.");
9913   // zvknha(SEW=32)/zvknhb(SEW=[32|64])
9919       report_fatal_error("SEW=64 needs Zvknhb to be enabled.");
9923       report_fatal_error("EGW should be greater than or equal to 4 * SEW.");
11171 // TODO: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
11246   // If this is SEW=8 and VLMAX is potentially more than 256, we need
11282   // Calculate VLMAX-1 for the desired SEW.
11288   // Splat VLMAX-1 taking care to handle SEW==64 on RV32.
12402   // If this is SEW=8 and VLMAX is unknown or more than 256, we need
12406   // NOTE: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
13351     // Custom-legalize an EXTRACT_VECTOR_ELT where XLEN<SEW, as the SEW element
13353     // With vmv.x.s, when SEW > XLEN, only the least-significant XLEN bits are
13355     // upper- and lower- halves of the SEW-bit vector element, slid down to the
17448 // n-levels TRUNCATE_VECTOR_VL to satisfy RVV's SEW*2->SEW truncate
19010       unsigned SEW = RISCVVType::decodeVSEW(VSEW);
19012       uint64_t MaxVL = Subtarget.getRealMaxVLen() / SEW;
19621 // Helper to find Masked Pseudo instruction from MC instruction, LMUL and SEW.
19623 lookupMaskedIntrinsic(uint16_t MCOpcode, RISCVII::VLMUL LMul, unsigned SEW) {
19625       RISCVVInversePseudosTable::getBaseInfo(MCOpcode, LMul, SEW);
19626   assert(Inverse && "Unexpected LMUL and SEW pair for instruction");
19629   assert(Masked && "Could not find masked instruction for LMUL and SEW pair");
22513     unsigned SEW = DL.getTypeSizeInBits(ResVTy->getElementType());
22518                                 NumElts * SEW / 8),
22526          ConstantInt::get(XLenTy, Log2_64(SEW))});
22585     unsigned SEW = DL.getTypeSizeInBits(InVTy->getElementType());
22590                                 NumElts * SEW / 8),
22605                                     ConstantInt::get(XLenTy, Log2_64(SEW))});