Lines Matching defs:LMUL
174 // Disable the smallest fractional LMUL types if ELEN is less than
1610 // The maximum VF is for the smallest element width with LMUL=8.
2378 llvm_unreachable("Invalid vector tuple type LMUL.");
2388 llvm_unreachable("Invalid LMUL.");
2409 llvm_unreachable("Invalid LMUL.");
2425 RISCVII::VLMUL LMUL = getLMUL(VT);
2426 if (LMUL == RISCVII::VLMUL::LMUL_F8 ||
2427 LMUL == RISCVII::VLMUL::LMUL_F4 ||
2428 LMUL == RISCVII::VLMUL::LMUL_F2 ||
2429 LMUL == RISCVII::VLMUL::LMUL_1) {
2434 if (LMUL == RISCVII::VLMUL::LMUL_2) {
2439 if (LMUL == RISCVII::VLMUL::LMUL_4) {
2518 "different LMUL.");
2523 // LMUL>1 register class down to the outgoing one. At each step we half
2524 // the LMUL:
2692 // We prefer to use LMUL=1 for VLEN sized types. Use fractional lmuls for
2693 // narrower types. The smallest fractional LMUL we support is 8/ELEN. Within
2694 // each fractional LMUL we support SEW between 8 and LMUL*ELEN.
2850 /// is generally quadratic in the number of vreg implied by LMUL. Note that
2857 /// vrgather.vi/vx may be linear in the number of vregs implied by LMUL,
2865 /// variants.) Slides may be linear in the number of vregs implied by LMUL,
2873 /// variants.) Slides may be linear in the number of vregs implied by LMUL,
3963 // Our main goal here is to reduce LMUL (and thus work) required to
4233 // being (at least) linear in LMUL. As a result, using the vslidedown
4234 // lowering for every element ends up being VL*LMUL..
5612 // at high LMUL, at the cost of not being able to fold a following select
5651 // may involve vector splitting if we're already at LMUL=8, or our
5652 // user-supplied maximum fixed-length LMUL.
5669 // requires less work and less register pressure at high LMUL, and creates
7300 // perform the vslideups at a smaller LMUL, limited to MF2.
8797 // the LMUL will be sufficient to hold the smaller type.
9060 // smallest subvector that the index fits in. This can be used to reduce LMUL
9128 // we're performing the scalar inserts and slideup on a smaller LMUL.
9134 // Do we know an upper bound on LMUL?
9378 // Reduce the LMUL of our slidedown and vmv.x.s to the smallest LMUL which
9398 // is linear in LMUL, performing N extracts using vslidedown becomes
9400 // seems to have the same problem (the store is linear in LMUL), but the
9534 SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT);
9542 SEW, LMUL);
9607 // fractional LMULs. The LMUL is choosen so that with SEW=8 the VLMax is
9610 // SEW and LMUL are better for the surrounding vector instructions.
9615 // The smallest LMUL is only valid for the smallest element width.
9618 // Determine the VF that corresponds to LMUL 1 for ElementWidth.
9727 // LMUL * VLEN should be greater than or equal to EGS * SEW
10577 // don't know which register of a LMUL group contains the specific subvector
10667 // We do this by lowering to an EXTRACT_SUBVECTOR grabbing the nearest LMUL=1
10670 // of that LMUL=1 type back into the larger vector (resolving to another
10672 // LMUL=1 type to avoid allocating a large register group to hold our
10817 // don't know which register of a LMUL group contains the specific subvector
10827 // Shrink down Vec so we're performing the slidedown on a smaller LMUL.
10903 // If the vector type is an LMUL-group type, extract a subvector equal to the
10907 // If VecVT has an LMUL > 1, then SubVecVT should have a smaller LMUL, and
10984 // If the VT is LMUL=8, we need to split and reassemble.
11020 // (instead of a vid, vmsne sequence) reduces LMUL, and allows the mask
11066 // If the VT is LMUL=8, we need to split and reassemble.
11171 // TODO: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
11197 // into LMUL * M1 vrgather.vvs, so we get O(LMUL) performance instead of
11198 // O(LMUL^2).
11249 // If this is LMUL=8, we have to split before can use vrgatherei16.vv.
11268 // Just promote the int type to i16 which will double the LMUL.
11273 // At LMUL > 1, do the index computation in 16 bits to reduce register
11522 // FIXME: We need to do vector splitting manually for LMUL=8 cases.
12406 // NOTE: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
12408 // If this is LMUL=8, we have to split before using vrgatherei16.vv.
12451 // Just promote the int type to i16 which will double the LMUL.
14847 // work and less register pressure at high LMUL, and creates smaller constants
19621 // Helper to find Masked Pseudo instruction from MC instruction, LMUL and SEW.
19626 assert(Inverse && "Unexpected LMUL and SEW pair for instruction");
19629 assert(Masked && "Could not find masked instruction for LMUL and SEW pair");
22022 // operations to correspond roughly to that threshold. LMUL>1 operations
22025 // combining will typically form larger LMUL operations from the LMUL1
22300 auto [LMUL, Fractional] = RISCVVType::decodeVLMUL(getLMUL(ContainerVT));
22303 return Factor * LMUL <= 8;