Lines Matching defs:VL

67       SDValue VL = CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT());
72       Result = CurDAG->getNode(Opc, DL, VT, CurDAG->getUNDEF(VT), Src, VL);
84       SDValue VL = N->getOperand(3);
115                        VL};
261   SDValue VL;
262   selectVLOp(Node->getOperand(CurOp++), VL);
263   Operands.push_back(VL);
341   ReplaceUses(SDValue(Node, 1), SDValue(Load, 1)); // VL
1704       SDValue VL;
1705       selectVLOp(Node->getOperand(3), VL);
1710                     CurDAG->getMachineNode(VMSetOpcode, DL, VT, VL, MaskSEW));
1719                                                  {Src1, Imm, VL, SEW}));
1726           CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}),
1729                                                {Cmp, Cmp, VL, MaskSEW}));
1803       SDValue VL;
1804       selectVLOp(Node->getOperand(5), VL);
1818                                            {Mask, MaskedOff, VL, MaskSEW}));
1827             CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}),
1830                                                  {Mask, Cmp, VL, MaskSEW}));
1846                               {MaskedOff, Src1, Imm, V0, VL, SEW, Glue}));
1857                                  {MaskedOff, Src1, Src2, V0, VL, SEW, Glue}),
1861                                                {Cmp, Mask, VL, MaskSEW}));
2415     SDValue VL;
2417       // We could deal with more VL if we update the VSETVLI insert pass to
2421       selectVLOp(Node->getOperand(2), VL);
2423       selectVLOp(Node->getOperand(2), VL);
2428     // If VL=1, then we don't need to do a strided load and can just do a
2430     bool IsStrided = !isOneConstant(VL);
2443     Operands.append({VL, SEW, PolicyOp, Ld->getChain()});
3488 // Select VL as a 5 bit immediate or a value that will become a register. This
3490 bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
3493     VL = CurDAG->getTargetConstant(C->getZExtValue(), SDLoc(N),
3497     VL = CurDAG->getSignedTargetConstant(RISCV::VLMaxSentinel, SDLoc(N),
3501     // All our VL operands use an operand that allows GPRNoX0 or an immediate
3505     VL = CurDAG->getSignedTargetConstant(RISCV::VLMaxSentinel, SDLoc(N),
3508     VL = N;
3600     // There's no passthru on these _VL nodes so any VL/mask is ok, since any
3788   // assume that it's all-ones? Same applies to its VL.
3888 // The resulting VL is the minimum of the two VLs.
3893   SDValue Passthru, False, True, VL, Mask, Glue;
3899   VL = N->getOperand(4);
3962     LoopWorklist.push_back(VL.getNode());
3991   SDValue OrigVL = VL;
3992   VL = GetMinVL(TrueVL, VL);
3993   if (!VL)
3998   // for these if we change the active elements (i.e. mask or VL).
4000   if (RISCVII::elementsDependOnVL(TrueBaseMCID.TSFlags) && (TrueVL != VL))
4026   // However, if the VL became smaller than what the vmerge had originally, then
4027   // elements past VL that were previously in the vmerge's body will have moved
4030   bool MergeVLShrunk = VL != OrigVL;
4054   Ops.append({VL, SEW, PolicyOp});
4073   // Replace another value of True. E.g. chain and VL.