Lines Matching defs:MBBI
45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
50 MachineBasicBlock::iterator MBBI, unsigned Opcode);
52 MachineBasicBlock::iterator MBBI);
54 MachineBasicBlock::iterator MBBI);
56 MachineBasicBlock::iterator MBBI);
58 MachineBasicBlock::iterator MBBI);
94 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
95 while (MBBI != E) {
96 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
97 Modified |= expandMI(MBB, MBBI, NMBBI);
98 MBBI = NMBBI;
105 MachineBasicBlock::iterator MBBI,
110 switch (MBBI->getOpcode()) {
112 return expandMV_FPR16INX(MBB, MBBI);
114 return expandMV_FPR32INX(MBB, MBBI);
116 return expandRV32ZdinxStore(MBB, MBBI);
118 return expandRV32ZdinxLoad(MBB, MBBI);
148 return expandCCOp(MBB, MBBI, NextMBBI);
157 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
166 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
173 MachineBasicBlock::iterator MBBI,
177 MachineInstr &MI = *MBBI;
193 BuildMI(MBB, MBBI, DL, TII->getBrCond(CC))
265 MachineBasicBlock::iterator MBBI,
267 DebugLoc DL = MBBI->getDebugLoc();
268 Register DstReg = MBBI->getOperand(0).getReg();
270 BuildMI(MBB, MBBI, DL, Desc, DstReg)
273 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
278 MachineBasicBlock::iterator MBBI) {
279 DebugLoc DL = MBBI->getDebugLoc();
282 MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
284 MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
286 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
287 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
290 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
295 MachineBasicBlock::iterator MBBI) {
296 DebugLoc DL = MBBI->getDebugLoc();
299 MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
301 MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
303 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
304 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
307 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
315 MachineBasicBlock::iterator MBBI) {
316 DebugLoc DL = MBBI->getDebugLoc();
319 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
321 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
323 auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
324 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
325 .addReg(MBBI->getOperand(1).getReg())
326 .add(MBBI->getOperand(2));
329 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
330 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
331 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
332 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
333 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
334 .add(MBBI->getOperand(1))
335 .add(MBBI->getOperand(2));
337 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
338 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
339 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
340 .add(MBBI->getOperand(1))
341 .addImm(MBBI->getOperand(2).getImm() + 4);
347 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
354 MBBI->eraseFromParent();
362 MachineBasicBlock::iterator MBBI) {
363 DebugLoc DL = MBBI->getDebugLoc();
366 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
368 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
374 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
377 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
378 .addReg(MBBI->getOperand(1).getReg())
379 .add(MBBI->getOperand(2));
382 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
383 auto Offset = MBBI->getOperand(2).getOffset();
385 MBBI->getOperand(2).setOffset(Offset + 4);
386 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
387 .addReg(MBBI->getOperand(1).getReg())
388 .add(MBBI->getOperand(2));
389 MBBI->getOperand(2).setOffset(Offset);
391 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
392 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
393 .addReg(MBBI->getOperand(1).getReg())
394 .addImm(MBBI->getOperand(2).getImm() + 4);
399 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
400 .addReg(MBBI->getOperand(1).getReg())
401 .add(MBBI->getOperand(2));
407 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
414 MBBI->eraseFromParent();
438 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
441 MachineBasicBlock::iterator MBBI,
445 MachineBasicBlock::iterator MBBI,
448 MachineBasicBlock::iterator MBBI,
451 MachineBasicBlock::iterator MBBI,
454 MachineBasicBlock::iterator MBBI,
457 MachineBasicBlock::iterator MBBI,
495 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
496 while (MBBI != E) {
497 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
498 Modified |= expandMI(MBB, MBBI, NMBBI);
499 MBBI = NMBBI;
506 MachineBasicBlock::iterator MBBI,
509 switch (MBBI->getOpcode()) {
511 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
513 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
515 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
517 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
519 return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
525 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
529 MachineInstr &MI = *MBBI;
541 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
545 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
557 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
559 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
564 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
567 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
572 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
575 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
580 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
582 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
587 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
590 MachineInstr &MI = *MBBI;
607 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
610 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
614 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
618 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
623 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)