Lines Matching defs:OutMI

122   bool lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
1056                                             MCInst &OutMI) {
1062   OutMI.setOpcode(RVV->BaseInstr);
1100       const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
1101       // Skip if the next operand in OutMI is not supposed to be tied. Unless it
1103       if (OutMCID.getOperandConstraint(OutMI.getNumOperands(), MCOI::TIED_TO) <
1150     OutMI.addOperand(MCOp);
1155   const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
1156   if (OutMI.getNumOperands() < OutMCID.getNumOperands()) {
1157     assert(OutMCID.operands()[OutMI.getNumOperands()].RegClass ==
1160     OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
1163   assert(OutMI.getNumOperands() == OutMCID.getNumOperands());
1167 bool RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
1168   if (lowerRISCVVMachineInstrToMCInst(MI, OutMI))
1171   OutMI.setOpcode(MI->getOpcode());
1176       OutMI.addOperand(MCOp);
1179   switch (OutMI.getOpcode()) {