Lines Matching defs:Val
49 static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
54 if (STI.hasFeature(RISCV::FeatureStdExtZbs) && isPowerOf2_64(Val) &&
55 (!isInt<32>(Val) || Val == 0x800)) {
56 Res.emplace_back(RISCV::BSETI, Log2_64(Val));
60 if (isInt<32>(Val)) {
68 int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
69 int64_t Lo12 = SignExtend64<12>(Val);
106 int64_t Lo12 = SignExtend64<12>(Val);
107 Val = (uint64_t)Val - (uint64_t)Lo12;
112 // Val might now be valid for LUI without needing a shift.
113 if (!isInt<32>(Val)) {
114 ShiftAmount = llvm::countr_zero((uint64_t)Val);
115 Val >>= ShiftAmount;
120 if (ShiftAmount > 12 && !isInt<12>(Val)) {
121 if (isInt<32>((uint64_t)Val << 12)) {
125 Val = (uint64_t)Val << 12;
126 } else if (isUInt<32>((uint64_t)Val << 12) &&
131 Val = ((uint64_t)Val << 12) | (0xffffffffull << 32);
136 // Try to use SLLI_UW for Val when it is uint32 but not int32.
137 if (isUInt<32>((uint64_t)Val) && !isInt<32>((uint64_t)Val) &&
141 Val = ((uint64_t)Val) | (0xffffffffull << 32);
146 generateInstSeqImpl(Val, STI, Res);
158 static unsigned extractRotateInfo(int64_t Val) {
160 unsigned LeadingOnes = llvm::countl_one((uint64_t)Val);
161 unsigned TrailingOnes = llvm::countr_one((uint64_t)Val);
167 unsigned UpperTrailingOnes = llvm::countr_one(Hi_32(Val));
168 unsigned LowerLeadingOnes = llvm::countl_one(Lo_32(Val));
176 static void generateInstSeqLeadingZeros(int64_t Val, const MCSubtargetInfo &STI,
178 assert(Val > 0 && "Expected postive val");
180 unsigned LeadingZeros = llvm::countl_zero((uint64_t)Val);
181 uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros;
213 uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
227 InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
229 generateInstSeqImpl(Val, STI, Res);
234 if ((Val & 0xfff) != 0 && (Val & 1) == 0 && Res.size() >= 2) {
235 unsigned TrailingZeros = llvm::countr_zero((uint64_t)Val);
236 int64_t ShiftedVal = Val >> TrailingZeros;
266 if ((Val & 0xfff) != 0 && (Val & 0x1800) == 0x1000) {
267 int64_t Imm12 = -(0x800 - (Val & 0xfff));
268 int64_t AdjustedVal = Val - Imm12;
281 if (Val > 0 && Res.size() > 2) {
282 generateInstSeqLeadingZeros(Val, STI, Res);
287 if (Val < 0 && Res.size() > 3) {
288 uint64_t InvertedVal = ~(uint64_t)Val;
303 int64_t LoVal = SignExtend64<32>(Val);
304 int64_t HiVal = SignExtend64<32>(Val >> 32);
319 uint64_t Lo = Val & 0x7fffffff;
320 uint64_t Hi = Val ^ Lo;
341 uint64_t Lo = Val | 0xffffffff80000000;
342 uint64_t Hi = Val ^ Lo;
363 if ((Val % 3) == 0 && isInt<32>(Val / 3)) {
366 } else if ((Val % 5) == 0 && isInt<32>(Val / 5)) {
369 } else if ((Val % 9) == 0 && isInt<32>(Val / 9)) {
375 generateInstSeqImpl(Val / Div, STI, TmpSeq);
382 int64_t Hi52 = ((uint64_t)Val + 0x800ull) & ~0xfffull;
383 int64_t Lo12 = SignExtend64<12>(Val);
397 // For Val that has zero Lo12 (implies Val equals to Hi52) should has
416 if (unsigned Rotate = extractRotateInfo(Val)) {
418 uint64_t NegImm12 = llvm::rotl<uint64_t>(Val, Rotate);
431 void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,
433 RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, STI);
468 InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,
470 int64_t LoVal = SignExtend64<32>(Val);
475 uint64_t Tmp = (uint64_t)Val - (uint64_t)LoVal;
492 if (STI.hasFeature(RISCV::FeatureStdExtZba) && Lo_32(Val) == Hi_32(Val)) {
501 int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI,
512 APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);