Lines Matching defs:STI

49 static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
51   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
54   if (STI.hasFeature(RISCV::FeatureStdExtZbs) && isPowerOf2_64(Val) &&
127                  STI.hasFeature(RISCV::FeatureStdExtZba)) {
138         STI.hasFeature(RISCV::FeatureStdExtZba)) {
146   generateInstSeqImpl(Val, STI, Res);
176 static void generateInstSeqLeadingZeros(int64_t Val, const MCSubtargetInfo &STI,
188   generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
200   generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
211   if (LeadingZeros == 32 && STI.hasFeature(RISCV::FeatureStdExtZba)) {
215     generateInstSeqImpl(LeadingOnesVal, STI, TmpSeq);
227 InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
229   generateInstSeqImpl(Val, STI, Res);
242         isInt<6>(ShiftedVal) && !STI.hasFeature(RISCV::TuneLUIADDIFusion);
244     generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
258   assert(STI.hasFeature(RISCV::Feature64Bit) &&
270     generateInstSeqImpl(AdjustedVal, STI, TmpSeq);
282     generateInstSeqLeadingZeros(Val, STI, Res);
290     generateInstSeqLeadingZeros(InvertedVal, STI, TmpSeq);
302   if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbkb)) {
307       generateInstSeqImpl(LoVal, STI, TmpSeq);
316   if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbs)) {
325       generateInstSeqImpl(Lo, STI, TmpSeq);
337   if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbs)) {
346     generateInstSeqImpl(Lo, STI, TmpSeq);
358   if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZba)) {
375       generateInstSeqImpl(Val / Div, STI, TmpSeq);
402         generateInstSeqImpl(Hi52 / Div, STI, TmpSeq);
414   if (Res.size() > 2 && (STI.hasFeature(RISCV::FeatureStdExtZbb) ||
415                          STI.hasFeature(RISCV::FeatureVendorXTHeadBb))) {
421       TmpSeq.emplace_back(STI.hasFeature(RISCV::FeatureStdExtZbb)
431 void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,
433   RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, STI);
468 InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,
489     return RISCVMatInt::generateInstSeq(LoVal, STI);
492   if (STI.hasFeature(RISCV::FeatureStdExtZba) && Lo_32(Val) == Hi_32(Val)) {
495     return RISCVMatInt::generateInstSeq(LoVal, STI);
501 int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI,
503   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
504   bool HasRVC = CompressionCost && (STI.hasFeature(RISCV::FeatureStdExtC) ||
505                                     STI.hasFeature(RISCV::FeatureStdExtZca));
515     InstSeq MatSeq = generateInstSeq(Chunk.getSExtValue(), STI);