Lines Matching defs:PVT

12735   MVT PVT = getPointerTy(MF->getDataLayout());
12736   assert((PVT == MVT::i64 || PVT == MVT::i32) &&
12779   const int64_t LabelOffset = 1 * PVT.getStoreSize();
12780   const int64_t TOCOffset   = 3 * PVT.getStoreSize();
12781   const int64_t BPOffset    = 4 * PVT.getStoreSize();
12784   const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
12867   MVT PVT = getPointerTy(MF->getDataLayout());
12868   assert((PVT == MVT::i64 || PVT == MVT::i32) &&
12872     (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
12875   unsigned FP  = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
12876   unsigned SP  = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
12878       (PVT == MVT::i64)
12885   const int64_t LabelOffset = 1 * PVT.getStoreSize();
12886   const int64_t SPOffset    = 2 * PVT.getStoreSize();
12887   const int64_t TOCOffset   = 3 * PVT.getStoreSize();
12888   const int64_t BPOffset    = 4 * PVT.getStoreSize();
12895   if (PVT == MVT::i64) {
12907   if (PVT == MVT::i64) {
12919   if (PVT == MVT::i64) {
12931   if (PVT == MVT::i64) {
12943   if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
12953           TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
12954   BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));