Lines Matching defs:IsPPC64

5254     SelectionDAG &DAG, MachineFunction &MF, bool IsPPC64, SDValue Arg,
5260   EVT VT = IsPPC64 ? MVT::i64 : MVT::i32;
5724   const bool IsPPC64 = Subtarget.isPPC64();
5764       Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
6865   const bool IsPPC64 = Subtarget.isPPC64();
6866   const unsigned PtrSize = IsPPC64 ? 8 : 4;
6889   const ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32;
6942     assert(IsPPC64 && "PPC32 should have split i64 values.");
6965         State.AllocateStack(IsPPC64 ? 8 : StoreSize, Align(4));
7102                                                     bool IsPPC64,
7105   assert((IsPPC64 || SVT != MVT::i64) &&
7114     return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7221   const bool IsPPC64 = Subtarget.isPPC64();
7222   const unsigned PtrByteSize = IsPPC64 ? 8 : 4;
7260           LocVT.SimpleTy, IsPPC64, Subtarget.hasP8Vector(), Subtarget.hasVSX());
7337                      getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
7351         assert(!IsPPC64 &&
7425           IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7476                        getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
7517     const unsigned NumGPArgRegs = std::size(IsPPC64 ? GPR_64 : GPR_32);
7527           IsPPC64 ? MF.addLiveIn(GPR_64[GPRIndex], &PPC::G8RCRegClass)
7576   const bool IsPPC64 = Subtarget.isPPC64();
7578   const unsigned PtrByteSize = IsPPC64 ? 8 : 4;
7603   const SDValue StackPtr = IsPPC64 ? DAG.getRegister(PPC::X1, MVT::i64)
7765         assert(!IsPPC64 &&
7809       assert(Arg.getValueType() == MVT::f64 && CFlags.IsVarArg && !IsPPC64 &&
17477   bool IsPPC64 = Subtarget.isPPC64();
17479   bool Is64Bit = IsPPC64 && VT == LLT::scalar(64);
17490   if ((IsPPC64 && Reg == PPC::R2) || Reg == PPC::R0)