Lines Matching defs:isPPC64
45 return STI.isPPC64() ? 16 : 8;
47 return STI.isPPC64() ? 16 : 4;
52 return STI.isPPC64() ? 40 : 20;
58 return STI.isPPC64() ? -8U : -4U;
62 if (STI.isAIXABI() || STI.isPPC64())
63 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
75 return STI.isPPC64() ? -16U : -8U;
79 return (STI.isAIXABI() && !STI.isPPC64()) ? 4 : 8;
243 if (Subtarget.isPPC64()) {
448 Register R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
449 Register R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12;
492 BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass :
544 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
573 if (!Subtarget.isELFv2ABI() || !Subtarget.isPPC64())
624 bool isPPC64 = Subtarget.isPPC64();
633 if (!isPPC64 && (!isInt<32>(FrameSize) || !isInt<32>(NegFrameSize)))
648 bool HasRedZone = isPPC64 || !isSVR4ABI;
652 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
654 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
655 Register LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
656 Register TOCReg = isPPC64 ? PPC::X2 : PPC::R2;
658 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
660 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
662 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
664 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
666 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
668 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
670 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
672 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
674 const MCInstrDesc &MoveFromCondRegInst = TII.get(isPPC64 ? PPC::MFCR8
676 const MCInstrDesc &StoreWordInst = TII.get(isPPC64 ? PPC::STW8 : PPC::STW);
678 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHSTP8 : PPC::HASHST8)
685 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
795 assert(isPPC64 && "V2 ABI is 64-bit only.");
924 TII.get(isPPC64 ? PPC::PROBED_STACKALLOC_64
940 if (isPPC64)
992 assert(!isPPC64 && "A red zone is always available on PPC64");
1202 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1240 bool isPPC64 = Subtarget.isPPC64();
1263 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1270 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
1271 const MCInstrDesc &CopyInst = TII.get(isPPC64 ? PPC::OR8 : PPC::OR);
1298 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::LI8 : PPC::LI), TempReg)
1301 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg)
1303 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::ORI8 : PPC::ORI), TempReg)
1314 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDU : PPC::STWU), SPReg)
1319 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)
1407 BuildMI(&MBB, DL, TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), ScratchReg)
1412 BuildMI(&MBB, DL, TII.get(isPPC64 ? PPC::CMPDI : PPC::CMPWI), CRReg)
1427 BuildMI(ProbeLoopBodyMBB, DL, TII.get(isPPC64 ? PPC::ADDI8 : PPC::ADDI),
1431 BuildMI(ProbeLoopBodyMBB, DL, TII.get(isPPC64 ? PPC::CMPDI : PPC::CMPWI),
1451 if (isPPC64)
1462 BuildMI(*CurrentMBB, {MI}, DL, TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF),
1467 BuildMI(*CurrentMBB, {MI}, DL, TII.get(isPPC64 ? PPC::ADD8 : PPC::ADD4),
1506 BuildMI(*CurrentMBB, {MI}, DL, TII.get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR))
1520 BuildMI(LoopMBB, DL, TII.get(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ))
1560 bool isPPC64 = Subtarget.isPPC64();
1570 bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
1574 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1576 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1578 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
1579 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1581 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
1583 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1585 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
1587 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1589 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1591 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1593 const MCInstrDesc& LoadWordInst = TII.get( isPPC64 ? PPC::LWZ8
1595 const MCInstrDesc& MoveToCRInst = TII.get( isPPC64 ? PPC::MTOCRF8
1598 TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHCHKP8 : PPC::HASHCHK8)
1996 const bool isPPC64 = Subtarget.isPPC64();
2004 FPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
2013 BPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
2030 SavedRegs.reset(isPPC64 ? PPC::X31 : PPC::R31);
2035 if (!needsFP(MF) && !SavedRegs.test(isPPC64 ? PPC::X31 : PPC::R31) &&
2038 (RegInfo->getBaseRegister(MF) == (isPPC64 ? PPC::X30 : PPC::R30)) &&
2040 SavedRegs.set(isPPC64 ? PPC::X31 : PPC::R31);
2063 Subtarget.isPPC64() ? 8 : Subtarget.isAIXABI() ? 4 : -4;
2242 const unsigned GPRegSize = Subtarget.isPPC64() ? 8 : 4;
2309 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC;
2569 bool is64Bit = Subtarget.isPPC64();
2816 if (Subtarget.isPPC64())