Lines Matching defs:SPReg
652 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
814 .addReg(SPReg);
828 .addReg(SPReg);
833 .addReg(SPReg);
838 .addReg(SPReg);
849 .addReg(SPReg);
867 .addReg(SPReg);
880 .addReg(SPReg);
896 .addReg(SPReg)
897 .addReg(SPReg);
935 .addReg(SPReg);
942 .addReg(SPReg)
947 .addReg(SPReg)
963 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
964 .addReg(SPReg, RegState::Kill)
965 .addReg(SPReg)
968 BuildMI(MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)
969 .addReg(SPReg)
971 .addReg(SPReg);
974 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
975 .addReg(SPReg, RegState::Kill)
976 .addReg(SPReg)
988 .addReg(SPReg);
994 // The negated frame size is in ScratchReg, and the SPReg has been
995 // decremented by the frame size: SPReg = old SPReg + ScratchReg.
1006 .addReg(SPReg);
1080 // Since the SPReg has been decreased by FrameSize, add it back to each
1086 .addReg(SPReg);
1091 .addReg(SPReg);
1096 .addReg(SPReg);
1098 .addReg(SPReg)
1169 .addReg(SPReg)
1170 .addReg(SPReg);
1263 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1314 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDU : PPC::STWU), SPReg)
1317 .addReg(SPReg);
1319 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)
1321 .addReg(SPReg)
1408 .addReg(SPReg)
1411 BuildMI(&MBB, DL, CopyInst, TempReg).addReg(SPReg).addReg(SPReg);
1453 .addReg(SPReg)
1458 .addReg(SPReg)
1465 .addReg(SPReg);
1476 BuildMI(*CurrentMBB, {MI}, DL, CopyInst, FPReg).addReg(SPReg).addReg(SPReg);
1497 // Restore using SPReg to calculate CFA.
1498 buildDefCFAReg(*CurrentMBB, {MI}, SPReg);
1531 // Restore using SPReg to calculate CFA.
1532 buildDefCFAReg(*ExitMBB, ExitMBB->begin(), SPReg);
1574 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1674 unsigned RBReg = SPReg;
1741 BuildMI(MBB, StackUpdateLoc, dl, AddImmInst, SPReg)
1742 .addReg(SPReg)
1767 .addReg(SPReg);
1783 .addReg(SPReg);
1794 if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
1802 assert(RBReg == SPReg && "Should be using SP as a base register");
1811 if (HasRedZone || RBReg == SPReg)
1814 .addReg(SPReg);
1833 if (RBReg != SPReg || SPAdd != 0) {
1837 BuildMI(MBB, MBBI, dl, OrInst, SPReg)
1841 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1855 .addReg(SPReg);
1877 .addReg(SPReg);
1893 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1894 .addReg(SPReg).addImm(CallerAllocatedAmt);
1902 .addReg(SPReg)